From 7772de25d07c977e41f8faa3bbf327033cd81c20 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Mon, 21 May 2018 21:41:02 +0000 Subject: [DAGCombine][X86][AArch64] Masked merge unfolding: vector edition. Summary: This **appears** to be the last missing piece for the masked merge pattern handling in the backend. This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]]. [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly. Previously, `andps`+`andnps` / `bsl` would be generated. (see `@out`) Now, they would no longer be generated (see `@in`), and we need to make sure that they are generated. Differential Revision: https://reviews.llvm.org/D46528 llvm-svn: 332904 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ---- 1 file changed, 4 deletions(-) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index fa4c1dd4aae..fc16a06bd99 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -5391,10 +5391,6 @@ SDValue DAGCombiner::unfoldMaskedMerge(SDNode *N) { EVT VT = N->getValueType(0); - // FIXME - if (VT.isVector()) - return SDValue(); - // There are 3 commutable operators in the pattern, // so we have to deal with 8 possible variants of the basic pattern. SDValue X, Y, M; -- cgit v1.2.3