From 73420b379585d67cd873549deff8658615b43ff2 Mon Sep 17 00:00:00 2001
From: Andrew Lenharth <andrewl@lenharth.org>
Date: Fri, 2 Dec 2005 04:56:24 +0000
Subject: cycle counter fix

llvm-svn: 24573
---
 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'llvm/lib/CodeGen')

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 0690c641db6..feaf890e950 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1193,6 +1193,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
     if (Tmp1 != Node->getOperand(0))
       Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1);
+
+    // Since rdcc produce two values, make sure to remember that we legalized
+    // both of them.
+    AddLegalizedOperand(SDOperand(Node, 0), Result);
+    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+    return Result.getValue(Op.ResNo);
     break;
 
   case ISD::TRUNCSTORE:
-- 
cgit v1.2.3