From 6b01d35497e21cbb6b61bf123bf0f52c0050515d Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Fri, 14 Dec 2018 20:14:12 +0000 Subject: [SDAG] Ignore chain operand in REG_SEQUENCE when emitting instructions llvm-svn: 349186 --- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index b51c23c6a74..da6d973e0b7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -652,6 +652,10 @@ void InstrEmitter::EmitRegSequence(SDNode *Node, const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); unsigned NumOps = Node->getNumOperands(); + // REG_SEQUENCE can "inherit" a chain from a subnode. + if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other) + --NumOps; // Ignore chain if it exists. + assert((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"); for (unsigned i = 1; i != NumOps; ++i) { -- cgit v1.2.3