From 3f5ce18658f0b6cc01853a02aede777d190ee52d Mon Sep 17 00:00:00 2001 From: Sanjoy Das Date: Tue, 12 Mar 2019 01:31:44 +0000 Subject: Reland "Relax constraints for reduction vectorization" Change from original commit: move test (that uses an X86 triple) into the X86 subdirectory. Original description: Gating vectorizing reductions on *all* fastmath flags seems unnecessary; `reassoc` should be sufficient. Reviewers: tvvikram, mkuper, kristof.beyls, sdesmalen, Ayal Reviewed By: sdesmalen Subscribers: dcaballe, huntergr, jmolloy, mcrosier, jlebar, bixia, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57728 llvm-svn: 355889 --- llvm/lib/CodeGen/ExpandReductions.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/ExpandReductions.cpp b/llvm/lib/CodeGen/ExpandReductions.cpp index f44d89156b6..34858883298 100644 --- a/llvm/lib/CodeGen/ExpandReductions.cpp +++ b/llvm/lib/CodeGen/ExpandReductions.cpp @@ -118,9 +118,11 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) { } if (!TTI->shouldExpandReduction(II)) continue; + FastMathFlags FMF = + isa(II) ? II->getFastMathFlags() : FastMathFlags{}; Value *Rdx = IsOrdered ? getOrderedReduction(Builder, Acc, Vec, getOpcode(ID), MRK) - : getShuffleReduction(Builder, Vec, getOpcode(ID), MRK); + : getShuffleReduction(Builder, Vec, getOpcode(ID), MRK, FMF); II->replaceAllUsesWith(Rdx); II->eraseFromParent(); Changed = true; -- cgit v1.2.3