From 3c1c4c0ee0628b22d09a6ec2b1fedd0a72c5ace3 Mon Sep 17 00:00:00 2001
From: Daniel Sanders <daniel_l_sanders@apple.com>
Date: Tue, 5 Dec 2017 05:52:07 +0000
Subject: Revert r319691: [globalisel][tablegen] Split atomic load/store into
 separate opcode and enable for AArch64.

Some concerns were raised with the direction. Revert while we discuss it and look into an alternative

llvm-svn: 319739
---
 llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp     | 21 ----------------
 llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 32 ------------------------
 2 files changed, 53 deletions(-)

(limited to 'llvm/lib/CodeGen')

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 774ea9877a7..e911085d0ad 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -345,16 +345,6 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
   unsigned Res = getOrCreateVReg(LI);
   unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
 
-  if (LI.getOrdering() != AtomicOrdering::NotAtomic) {
-    MIRBuilder.buildAtomicLoad(
-        Res, Addr,
-        *MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
-                                  Flags, DL->getTypeStoreSize(LI.getType()),
-                                  getMemOpAlignment(LI), AAMDNodes(), nullptr,
-                                  LI.getSyncScopeID(), LI.getOrdering()));
-    return true;
-  }
-
   MIRBuilder.buildLoad(
       Res, Addr,
       *MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
@@ -376,17 +366,6 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
   unsigned Val = getOrCreateVReg(*SI.getValueOperand());
   unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
 
-  if (SI.getOrdering() != AtomicOrdering::NotAtomic) {
-    MIRBuilder.buildAtomicStore(
-        Val, Addr,
-        *MF->getMachineMemOperand(
-            MachinePointerInfo(SI.getPointerOperand()), Flags,
-            DL->getTypeStoreSize(SI.getValueOperand()->getType()),
-            getMemOpAlignment(SI), AAMDNodes(), nullptr, SI.getSyncScopeID(),
-            SI.getOrdering()));
-    return true;
-  }
-
   MIRBuilder.buildStore(
       Val, Addr,
       *MF->getMachineMemOperand(
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index fbcb14d5252..62c396e6cdf 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -295,8 +295,6 @@ MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
                                                 MachineMemOperand &MMO) {
   assert(MRI->getType(Res).isValid() && "invalid operand type");
   assert(MRI->getType(Addr).isPointer() && "invalid operand type");
-  assert(MMO.getOrdering() == AtomicOrdering::NotAtomic &&
-         "invalid atomic ordering");
 
   return buildInstr(TargetOpcode::G_LOAD)
       .addDef(Res)
@@ -308,8 +306,6 @@ MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
                                                  MachineMemOperand &MMO) {
   assert(MRI->getType(Val).isValid() && "invalid operand type");
   assert(MRI->getType(Addr).isPointer() && "invalid operand type");
-  assert(MMO.getOrdering() == AtomicOrdering::NotAtomic &&
-         "invalid atomic ordering");
 
   return buildInstr(TargetOpcode::G_STORE)
       .addUse(Val)
@@ -317,34 +313,6 @@ MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
       .addMemOperand(&MMO);
 }
 
-MachineInstrBuilder MachineIRBuilder::buildAtomicLoad(unsigned Res,
-                                                      unsigned Addr,
-                                                      MachineMemOperand &MMO) {
-  assert(MRI->getType(Res).isValid() && "invalid operand type");
-  assert(MRI->getType(Addr).isPointer() && "invalid operand type");
-  assert(MMO.getOrdering() != AtomicOrdering::NotAtomic &&
-         "invalid atomic ordering");
-
-  return buildInstr(TargetOpcode::G_ATOMIC_LOAD)
-      .addDef(Res)
-      .addUse(Addr)
-      .addMemOperand(&MMO);
-}
-
-MachineInstrBuilder MachineIRBuilder::buildAtomicStore(unsigned Val,
-                                                       unsigned Addr,
-                                                       MachineMemOperand &MMO) {
-  assert(MRI->getType(Val).isValid() && "invalid operand type");
-  assert(MRI->getType(Addr).isPointer() && "invalid operand type");
-  assert(MMO.getOrdering() != AtomicOrdering::NotAtomic &&
-         "invalid atomic ordering");
-
-  return buildInstr(TargetOpcode::G_ATOMIC_STORE)
-      .addUse(Val)
-      .addUse(Addr)
-      .addMemOperand(&MMO);
-}
-
 MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
                                                  unsigned CarryOut,
                                                  unsigned Op0, unsigned Op1,
-- 
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