From 1cde1f8d5e893678b1aabe0ef219adf9ad05019e Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 16 Jun 2008 22:52:53 +0000 Subject: Do not issue identity copies. llvm-svn: 52373 --- llvm/lib/CodeGen/LowerSubregs.cpp | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/LowerSubregs.cpp b/llvm/lib/CodeGen/LowerSubregs.cpp index 0710a353006..296e6d45c34 100644 --- a/llvm/lib/CodeGen/LowerSubregs.cpp +++ b/llvm/lib/CodeGen/LowerSubregs.cpp @@ -108,15 +108,20 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { DOUT << "subreg: CONVERTING: " << *MI; - // Insert sub-register copy - const TargetRegisterClass *TRC0 = TRI.getPhysicalRegisterRegClass(DstSubReg); - const TargetRegisterClass *TRC1 = TRI.getPhysicalRegisterRegClass(InsReg); - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + if (DstSubReg == InsReg) { + // No need to insert an identify copy instruction. + DOUT << "subreg: eliminated!"; + } else { + // Insert sub-register copy + const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); + const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); #ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); + MachineBasicBlock::iterator dMI = MI; + DOUT << "subreg: " << *(--dMI); #endif + } DOUT << "\n"; MBB->remove(MI); @@ -149,15 +154,19 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { DOUT << "subreg: CONVERTING: " << *MI; - // Insert sub-register copy - const TargetRegisterClass *TRC0 = TRI.getPhysicalRegisterRegClass(DstSubReg); - const TargetRegisterClass *TRC1 = TRI.getPhysicalRegisterRegClass(InsReg); - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); - + if (DstSubReg == InsReg) { + // No need to insert an identify copy instruction. + DOUT << "subreg: eliminated!"; + } else { + // Insert sub-register copy + const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); + const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); #ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); + MachineBasicBlock::iterator dMI = MI; + DOUT << "subreg: " << *(--dMI); #endif + } DOUT << "\n"; MBB->remove(MI); -- cgit v1.2.3