From 133b1cdf087963dfa65151c3be23d6c47462b432 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 26 Jun 2018 15:39:16 +0000 Subject: [DAGCombiner] Pull out VT bitwidth in visitSDIV. NFCI. llvm-svn: 335617 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7f7f097b8f3..f6dbd747453 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3004,6 +3004,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); EVT VT = N->getValueType(0); + unsigned BitWidth = VT.getScalarSizeInBits(); // fold vector ops if (VT.isVector()) @@ -3072,16 +3073,15 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) { // Create constants that are functions of the shift amount value. EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType()); - SDValue Bits = DAG.getConstant(VT.getScalarSizeInBits(), DL, ShiftAmtTy); + SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy); SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1); C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy); SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1); if (!isConstantOrConstantVector(Inexact)) return SDValue(); // Splat the sign bit into the register - SDValue Sign = DAG.getNode( - ISD::SRA, DL, VT, N0, - DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, ShiftAmtTy)); + SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0, + DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy)); AddToWorklist(Sign.getNode()); // Add (N0 < 0) ? abs2 - 1 : 0; -- cgit v1.2.3