From 532815dd5c54b9ee7d16cf4a437e82bab39c99ad Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 30 Oct 2019 11:04:53 +0100 Subject: [ARM][AArch64][DebugInfo] Improve call site instruction interpretation Extend the describeLoadedValue() with support for target specific ARM and AArch64 instructions interpretation. The patch provides specialization for ADD and SUB operations that include a register and an immediate/offset operand. Some of the instructions can operate with global string addresses or constant pool indexes but such cases are omitted since we currently lack flexible support for processing such operands at DWARF production stage. Patch by Nikola Prica Differential Revision: https://reviews.llvm.org/D67556 --- llvm/lib/CodeGen/TargetInstrInfo.cpp | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'llvm/lib/CodeGen/TargetInstrInfo.cpp') diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index d99b2b0e997..88fbfcb7784 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -1123,13 +1123,15 @@ bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, Optional TargetInstrInfo::describeLoadedValue(const MachineInstr &MI) const { const MachineFunction *MF = MI.getMF(); - const MachineOperand *Op = nullptr; - DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});; + DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {}); const MachineOperand *SrcRegOp, *DestRegOp; + int64_t Offset; if (isCopyInstr(MI, SrcRegOp, DestRegOp)) { - Op = SrcRegOp; - return ParamLoadedValue(*Op, Expr); + return ParamLoadedValue(*SrcRegOp, Expr); + } else if (isAddImmediate(MI, DestRegOp, SrcRegOp, Offset)) { + Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset); + return ParamLoadedValue(*SrcRegOp, Expr); } return None; -- cgit v1.2.3