From 2ff0b0e6812e10538b974263b3b972bda184904f Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 26 Feb 2008 08:03:41 +0000 Subject: This is possible: vr1 = extract_subreg vr2, 3 ... vr3 = extract_subreg vr1, 2 The end result is vr3 is equal to vr2 with subidx 2. llvm-svn: 47592 --- llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp') diff --git a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp index ba026d7daf7..c723c9eeae1 100644 --- a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -457,8 +457,14 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, O.setSubReg(0); } else { unsigned OldSubIdx = O.getSubReg(); - assert((!SubIdx || !OldSubIdx) && "Conflicting sub-register index!"); - if (SubIdx) + // Sub-register indexes goes from small to large. e.g. + // RAX: 0 -> AL, 1 -> AH, 2 -> AX, 3 -> EAX + // EAX: 0 -> AL, 1 -> AH, 2 -> AX + // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose + // sub-register 2 is also AX. + if (SubIdx && OldSubIdx && SubIdx != OldSubIdx) + assert(OldSubIdx < SubIdx && "Conflicting sub-register index!"); + else if (SubIdx) O.setSubReg(SubIdx); O.setReg(DstReg); } -- cgit v1.2.3