From c9a67a2b6d65b15ce3aae9ec00eda255751d851d Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 24 Mar 2014 16:07:28 +0000 Subject: SelectionDAG: Allow promotion of SELECT nodes from float to int types And vice-versa, as long as the types are the same width. There are a few R600 tests that will cover this. llvm-svn: 204616 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'llvm/lib/CodeGen/SelectionDAG') diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 6297774484f..74c01cae437 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3990,7 +3990,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) { } case ISD::SELECT: { unsigned ExtOp, TruncOp; - if (Node->getValueType(0).isVector()) { + if (Node->getValueType(0).isVector() || + Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) { ExtOp = ISD::BITCAST; TruncOp = ISD::BITCAST; } else if (Node->getValueType(0).isInteger()) { -- cgit v1.2.3