From c0bb959591aab5fb5088b85fbb5a97865ab95b5b Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Fri, 13 Mar 2009 20:42:20 +0000 Subject: Fix FastISel's assumption that i1 values are always zero-extended by inserting explicit zero extensions where necessary. Included is a testcase where SelectionDAG produces a virtual register holding an i1 value which FastISel previously mistakenly assumed to be zero-extended. llvm-svn: 66941 --- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'llvm/lib/CodeGen/SelectionDAG') diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 229376d293c..3523dda97ea 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -497,7 +497,14 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { if (!InputReg) // Unhandled operand. Halt "fast" selection and bail. return false; - + + // If the operand is i1, arrange for the high bits in the register to be zero. + if (I->getOperand(0)->getType() == Type::Int1Ty) { + InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); + if (!InputReg) + return false; + } + unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opcode, @@ -970,3 +977,9 @@ unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, } return ResultReg; } + +/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op +/// with all but the least significant bit set to zero. +unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { + return FastEmit_ri(VT, VT, ISD::AND, Op, 1); +} -- cgit v1.2.3