From c075acbb54f39e7c971c34505847f59428eb0d14 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Wed, 6 Jan 2010 00:23:35 +0000 Subject: The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 order. llvm-svn: 92810 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/lib/CodeGen/SelectionDAG') diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 4d51f0c13e8..1ad7919962b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1129,8 +1129,8 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { // Prefer an ordering where the lower the non-zero order number, the higher // the preference. - if (LOrder && ROrder && LOrder != ROrder) - return LOrder < ROrder; + if ((LOrder || ROrder) && LOrder != ROrder) + return LOrder != 0 && (LOrder < ROrder || ROrder == 0); unsigned LPriority = SPQ->getNodePriority(left); unsigned RPriority = SPQ->getNodePriority(right); -- cgit v1.2.3