From 605a840747be60e2813137c94ae22d27a2f74564 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sat, 11 May 2019 20:56:05 +0000
Subject: [DAG] Add SimplifyDemandedBits support for BITREVERSE

Pulled out of D58017 while I continue to investigate the BSWAP regression on PPC

llvm-svn: 360534
---
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'llvm/lib/CodeGen/SelectionDAG')

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 093778add49..502913886e3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1268,6 +1268,16 @@ bool TargetLowering::SimplifyDemandedBits(
     }
     break;
   }
+  case ISD::BITREVERSE: {
+    SDValue Src = Op.getOperand(0);
+    APInt DemandedSrcBits = DemandedBits.reverseBits();
+    if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
+                             Depth + 1))
+      return true;
+    Known.One = Known2.One.reverseBits();
+    Known.Zero = Known2.Zero.reverseBits();
+    break;
+  }
   case ISD::SIGN_EXTEND_INREG: {
     SDValue Op0 = Op.getOperand(0);
     EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
-- 
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