From 48f75ad67813037ea12d5d10d887ef1014d9c307 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Mon, 18 Apr 2011 07:00:40 +0000
Subject: while we're at it, handle 'sdiv exact' of a power of 2 also, this
 fixes a few rejects on c++ iterator loops.

llvm-svn: 129694
---
 llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'llvm/lib/CodeGen/SelectionDAG')

diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index d3a721f8754..76e9a7cac2d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -360,6 +360,14 @@ bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
   if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
     uint64_t Imm = CI->getZExtValue();
     
+    // Transform "sdiv exact X, 8" -> "sra X, 3".
+    if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
+        cast<BinaryOperator>(I)->isExact() &&
+        isPowerOf2_64(Imm)) {
+      Imm = Log2_64(Imm);
+      ISDOpcode = ISD::SRA;
+    }
+    
     unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
                                       Op0IsKill, Imm, VT.getSimpleVT());
     if (ResultReg == 0) return false;
-- 
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