From c1d1944053fa1b86c2d8d626fa740d4100298fa3 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 7 Jul 2018 17:30:06 +0000 Subject: [DAGCombiner] Add EXTRACT_SUBVECTOR to SimplifyDemandedVectorElts As discussed on PR37989, this patch adds EXTRACT_SUBVECTOR handling to TargetLowering::SimplifyDemandedVectorElts and calls it from DAGCombiner::visitEXTRACT_SUBVECTOR. Differential Revision: https://reviews.llvm.org/D48825 llvm-svn: 336490 --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp') diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 6e829a35f7c..f1526a4ae46 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1479,6 +1479,25 @@ bool TargetLowering::SimplifyDemandedVectorElts( KnownZero.insertBits(SubZero, SubIdx); break; } + case ISD::EXTRACT_SUBVECTOR: { + if (!isa(Op.getOperand(1))) + break; + SDValue Src = Op.getOperand(0); + unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); + const APInt& Idx = cast(Op.getOperand(1))->getAPIntValue(); + if (Idx.uge(NumSrcElts - NumElts)) + break; + // Offset the demanded elts by the subvector index. + uint64_t SubIdx = Idx.getZExtValue(); + APInt SrcElts = DemandedElts.zext(NumSrcElts).shl(SubIdx); + APInt SrcUndef, SrcZero; + if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO, + Depth + 1)) + return true; + KnownUndef = SrcUndef.extractBits(NumElts, SubIdx); + KnownZero = SrcZero.extractBits(NumElts, SubIdx); + break; + } case ISD::INSERT_VECTOR_ELT: { SDValue Vec = Op.getOperand(0); SDValue Scl = Op.getOperand(1); -- cgit v1.2.3