From ff310737e5d5cbb5e29637f9d9f2c8a31a60afc8 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Thu, 28 Oct 2010 06:47:08 +0000
Subject: Re-commit 117518 and 117519 now that ARM MC test failures are out of
 the way.

llvm-svn: 117531
---
 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp')

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 0ffb4da0f36..d34a52d8014 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -454,6 +454,9 @@ void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use,
     return;
 
   unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
+  if (Use->isMachineOpcode())
+    // Adjust the use operand index by num of defs.
+    OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
   int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
   if (Latency >= 0)
     dep.setLatency(Latency);
-- 
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