From 61d21b1f3ca8e8d8fb3b28aa6dbebe73592d944c Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Tue, 30 Aug 2005 17:21:17 +0000
Subject: Fix FreeBench/fourinarow with the dag isel, by not adding a bogus
 result to SHIFT_PARTS nodes

llvm-svn: 23151
---
 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

(limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp')

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index db3b33abc51..758fd2de8d6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2388,10 +2388,7 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
   Ops.push_back(LHSL);
   Ops.push_back(LHSH);
   Ops.push_back(Amt);
-  std::vector<MVT::ValueType> VTs;
-  VTs.push_back(LHSL.getValueType());
-  VTs.push_back(LHSH.getValueType());
-  VTs.push_back(Amt.getValueType());
+  std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
   Lo = DAG.getNode(NodeOp, VTs, Ops);
   Hi = Lo.getValue(1);
 }
-- 
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