From 4816b18d863f351542fa5564ac4d0068985d7bff Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Wed, 26 Aug 2015 20:46:49 +0000 Subject: FastISel: Avoid adding a successor block twice for degenerate IR. This fixes http://llvm.org/PR24581 Differential Revision: http://reviews.llvm.org/D12350 llvm-svn: 246074 --- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'llvm/lib/CodeGen/SelectionDAG/FastISel.cpp') diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index d5011d2d62d..13b097cfc60 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1415,7 +1415,11 @@ void FastISel::finishCondBranch(const BasicBlock *BranchBB, if (FuncInfo.BPI) BranchWeight = FuncInfo.BPI->getEdgeWeight(BranchBB, TrueMBB->getBasicBlock()); - FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight); + // Add TrueMBB as successor unless it is equal to the FalseMBB: This can + // happen in degenerate IR and MachineIR forbids to have a block twice in the + // successor/predecessor lists. + if (TrueMBB != FalseMBB) + FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight); fastEmitBranch(FalseMBB, DbgLoc); } -- cgit v1.2.3