From 1d028a364d6fcee53f163ad2d3fa754a7fb860f5 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Sat, 14 Jan 2012 02:17:12 +0000 Subject: misched: Added ScheduleDAGInstrs::IsPostRA llvm-svn: 148172 --- llvm/lib/CodeGen/ScheduleDAGInstrs.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'llvm/lib/CodeGen/ScheduleDAGInstrs.h') diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.h b/llvm/lib/CodeGen/ScheduleDAGInstrs.h index a6233d34821..f3932892563 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.h +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.h @@ -104,10 +104,13 @@ namespace llvm { const MachineFrameInfo *MFI; const InstrItineraryData *InstrItins; - /// Defs, Uses - Remember where defs and uses of each physical register - /// are as we iterate upward through the instructions. This is allocated - /// here instead of inside BuildSchedGraph to avoid the need for it to be - /// initialized and destructed for each block. + /// isPostRA flag indicates vregs cannot be present. + bool IsPostRA; + + /// Defs, Uses - Remember where defs and uses of each register are as we + /// iterate upward through the instructions. This is allocated here instead + /// of inside BuildSchedGraph to avoid the need for it to be initialized and + /// destructed for each block. std::vector > Defs; std::vector > Uses; @@ -136,7 +139,8 @@ namespace llvm { explicit ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo &mli, - const MachineDominatorTree &mdt); + const MachineDominatorTree &mdt, + bool IsPostRAFlag); virtual ~ScheduleDAGInstrs() {} -- cgit v1.2.3