From 5a22df498e856b96018d66cdaeeb2e4c27be7b6b Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Thu, 5 Dec 2013 17:56:02 +0000 Subject: MI-Sched: Model "reserved" processor resources. This allows a target to use MI-Sched as an in-order scheduler that will model strict resource conflicts without defining a processor itinerary. Instead, the target can now use the new per-operand machine model and define in-order resources with BufferSize=0. For example, this would allow restricting the type of operations that can be formed into a dispatch group. (Normally NumMicroOps is sufficient to enforce dispatch groups). If the intent is to model latency in in-order pipeline, as opposed to resource conflicts, then a resource with BufferSize=1 should be defined instead. This feature is only casually tested as there are no in-tree targets using it yet. However, Hal will be experimenting with POWER7. llvm-svn: 196517 --- llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'llvm/lib/CodeGen/ScheduleDAGInstrs.cpp') diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index eeae6ec03d8..977b8f0b41d 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -697,9 +697,15 @@ void ScheduleDAGInstrs::initSUnits() { for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC), PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) { - if (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize == 1) { + switch (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize) { + case 0: + SU->hasReservedResource = true; + break; + case 1: SU->isUnbuffered = true; break; + default: + break; } } } -- cgit v1.2.3