From 830b20344bdd3f8790bb913b9e699a3fa5f446f6 Mon Sep 17 00:00:00 2001 From: Oliver Stannard Date: Wed, 3 Jul 2019 09:58:52 +0000 Subject: [ARM] Thumb2: favor R4-R7 over R12/LR in allocation order when opt for minsize For Thumb2, we prefer low regs (costPerUse = 0) to allow narrow encoding. However, current allocation order is like: R0-R3, R12, LR, R4-R11 As a result, a lot of instructs that use R12/LR will be wide instrs. This patch changes the allocation order to: R0-R7, R12, LR, R8-R11 for thumb2 and -Osize. In most cases, there is no extra push/pop instrs as they will be folded into existing ones. There might be slight performance impact due to more stack usage, so we only enable it when opt for min size. https://reviews.llvm.org/D30324 llvm-svn: 365014 --- llvm/lib/CodeGen/RegisterClassInfo.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'llvm/lib/CodeGen/RegisterClassInfo.cpp') diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp index 3d6687ef7b8..530e0cccf1d 100644 --- a/llvm/lib/CodeGen/RegisterClassInfo.cpp +++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp @@ -90,6 +90,7 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { assert(RC && "no register class given"); RCInfo &RCI = RegClass[RC->getID()]; + auto &STI = MF->getSubtarget(); // Raw register count, including all reserved regs. unsigned NumRegs = RC->getNumRegs(); @@ -114,7 +115,8 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { unsigned Cost = TRI->getCostPerUse(PhysReg); MinCost = std::min(MinCost, Cost); - if (CalleeSavedAliases[PhysReg]) + if (CalleeSavedAliases[PhysReg] && + !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) // PhysReg aliases a CSR, save it for later. CSRAlias.push_back(PhysReg); else { -- cgit v1.2.3