From 2150542af9c47a6c6614ec5900f7eb021211d8b5 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 2 Jun 2004 05:57:12 +0000 Subject: Adjust to new TargetMachine interface llvm-svn: 13956 --- llvm/lib/CodeGen/RegAllocSimple.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/lib/CodeGen/RegAllocSimple.cpp') diff --git a/llvm/lib/CodeGen/RegAllocSimple.cpp b/llvm/lib/CodeGen/RegAllocSimple.cpp index 1b7f5471b42..4e825b233e3 100644 --- a/llvm/lib/CodeGen/RegAllocSimple.cpp +++ b/llvm/lib/CodeGen/RegAllocSimple.cpp @@ -159,7 +159,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // a preliminary pass that will invalidate any registers that // are used by the instruction (including implicit uses) unsigned Opcode = MI->getOpcode(); - const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode); + const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode); const unsigned *Regs = Desc.ImplicitUses; while (*Regs) RegsUsed[*Regs++] = true; @@ -184,7 +184,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { if (op.isDef()) { - if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) { + if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) { physReg = getFreeReg(virtualReg); } else { // must be same register number as the first operand -- cgit v1.2.3