From 0d1e9a8e0401048b5619dd46afb744af7b028aff Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Fri, 3 Oct 2008 15:45:36 +0000 Subject: Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006 --- llvm/lib/CodeGen/RegAllocSimple.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/lib/CodeGen/RegAllocSimple.cpp') diff --git a/llvm/lib/CodeGen/RegAllocSimple.cpp b/llvm/lib/CodeGen/RegAllocSimple.cpp index 87b09a2a0dc..da729ae8dfc 100644 --- a/llvm/lib/CodeGen/RegAllocSimple.cpp +++ b/llvm/lib/CodeGen/RegAllocSimple.cpp @@ -190,7 +190,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { for (int i = MI->getNumOperands() - 1; i >= 0; --i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() && + if (MO.isReg() && MO.getReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned virtualReg = (unsigned) MO.getReg(); DOUT << "op: " << MO << "\n"; @@ -209,7 +209,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // must be same register number as the source operand that is // tied to. This maps a = b + c into b = b + c, and saves b into // a's spot. - assert(MI->getOperand(TiedOp).isRegister() && + assert(MI->getOperand(TiedOp).isReg() && MI->getOperand(TiedOp).getReg() && MI->getOperand(TiedOp).isUse() && "Two address instruction invalid!"); -- cgit v1.2.3