From 7366fa1aa6d69a63e016abe7baec035690797f5a Mon Sep 17 00:00:00 2001 From: "Vikram S. Adve" Date: Tue, 27 May 2003 00:05:23 +0000 Subject: (1) Added special register class containing (for now) %fsr. Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. (3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly() and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". llvm-svn: 6341 --- llvm/lib/CodeGen/RegAllocLocal.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'llvm/lib/CodeGen/RegAllocLocal.cpp') diff --git a/llvm/lib/CodeGen/RegAllocLocal.cpp b/llvm/lib/CodeGen/RegAllocLocal.cpp index 80100445a46..fed05b7dbbc 100644 --- a/llvm/lib/CodeGen/RegAllocLocal.cpp +++ b/llvm/lib/CodeGen/RegAllocLocal.cpp @@ -489,7 +489,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // Loop over all of the operands of the instruction, spilling registers that // are defined, and marking explicit destinations in the PhysRegsUsed map. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if ((MI->getOperand(i).opIsDef() || MI->getOperand(i).opIsDefAndUse()) && + if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse()) && MI->getOperand(i).isPhysicalRegister()) { unsigned Reg = MI->getOperand(i).getAllocatedRegNum(); spillPhysReg(MBB, I, Reg); // Spill any existing value in the reg @@ -512,8 +512,8 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // we need to scavenge a register. // for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if (MI->getOperand(i).opIsDef() && - MI->getOperand(i).isVirtualRegister()) { + if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse()) + && MI->getOperand(i).isVirtualRegister()) { unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum(); unsigned DestPhysReg; -- cgit v1.2.3