From 2a767c0d2602b5ecc2cd7b242b1bf91be64e4c49 Mon Sep 17 00:00:00 2001
From: Dan Gohman <gohman@apple.com>
Date: Wed, 12 Aug 2009 01:44:20 +0000
Subject: This logic was accidentally inverted in r78767.

llvm-svn: 78773
---
 llvm/lib/CodeGen/PostRASchedulerList.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')

diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp
index 27c73a75951..f3dfb01ff12 100644
--- a/llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -532,9 +532,9 @@ SchedulePostRATDList::findSuitableFreeRegister(unsigned AntiDepReg,
            "Kill and Def maps aren't consistent for AntiDepReg!");
     assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) &&
            "Kill and Def maps aren't consistent for NewReg!");
-    if (KillIndices[NewReg] == ~0u &&
-        Classes[NewReg] != reinterpret_cast<TargetRegisterClass *>(-1) &&
-        KillIndices[AntiDepReg] <= DefIndices[NewReg])
+    if (KillIndices[NewReg] != ~0u ||
+        Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
+        KillIndices[AntiDepReg] > DefIndices[NewReg])
       continue;
     return NewReg;
   }
-- 
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