From e61c7a3958e70edd92f9beb2f8da2a26cc5b43d4 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Sat, 16 May 2009 07:25:20 +0000 Subject: Verify that explicit definitions in the TargetInstrDesc are matched by explicit register define operands. llvm-svn: 71933 --- llvm/lib/CodeGen/MachineVerifier.cpp | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp') diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 25549b0269b..4244b2178b8 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -327,6 +327,18 @@ void MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { const MachineInstr *MI = MO->getParent(); + const TargetInstrDesc &TI = MI->getDesc(); + + // The first TI.NumDefs operands must be explicit register defines + if (MONum < TI.getNumDefs()) { + if (!MO->isReg()) + report("Explicit definition must be a register", MO, MONum); + else if (!MO->isDef()) + report("Explicit definition marked as use", MO, MONum); + else if (MO->isImplicit()) + report("Explicit definition marked as implicit", MO, MONum); + } + switch (MO->getType()) { case MachineOperand::MO_Register: { const unsigned Reg = MO->getReg(); @@ -374,7 +386,6 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) } // Check register classes. - const TargetInstrDesc &TI = MI->getDesc(); if (MONum < TI.getNumOperands() && !MO->isImplicit()) { const TargetOperandInfo &TOI = TI.OpInfo[MONum]; unsigned SubIdx = MO->getSubReg(); -- cgit v1.2.3