From 6cc775f905a850905f9f437d1f67b99ab3f821b1 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 28 Jun 2011 19:10:37 +0000 Subject: - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021 --- llvm/lib/CodeGen/MachineLICM.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'llvm/lib/CodeGen/MachineLICM.cpp') diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp index cfd0325ee9a..28a81e18819 100644 --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -1018,9 +1018,9 @@ MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) { /*UnfoldStore=*/false, &LoadRegIndex); if (NewOpc == 0) return 0; - const TargetInstrDesc &TID = TII->get(NewOpc); - if (TID.getNumDefs() != 1) return 0; - const TargetRegisterClass *RC = TII->getRegClass(TID, LoadRegIndex, TRI); + const MCInstrDesc &MID = TII->get(NewOpc); + if (MID.getNumDefs() != 1) return 0; + const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI); // Ok, we're unfolding. Create a temporary register and do the unfold. unsigned Reg = MRI->createVirtualRegister(RC); -- cgit v1.2.3