From 9fab370d79eb8c09bff29a8c0744060a15d63607 Mon Sep 17 00:00:00 2001 From: Alex Lorenz Date: Tue, 14 Jul 2015 21:24:41 +0000 Subject: MIR Serialization: Serialize the machine basic block live in registers. llvm-svn: 242204 --- llvm/lib/CodeGen/MIRParser/MIParser.cpp | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'llvm/lib/CodeGen/MIRParser/MIParser.cpp') diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index dec06bc9cc8..c00011288a6 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -78,6 +78,7 @@ public: bool parse(MachineInstr *&MI); bool parseMBB(MachineBasicBlock *&MBB); + bool parseNamedRegister(unsigned &Reg); bool parseRegister(unsigned &Reg); bool parseRegisterFlag(unsigned &Flags); @@ -215,6 +216,18 @@ bool MIParser::parseMBB(MachineBasicBlock *&MBB) { return false; } +bool MIParser::parseNamedRegister(unsigned &Reg) { + lex(); + if (Token.isNot(MIToken::NamedRegister)) + return error("expected a named register"); + if (parseRegister(Reg)) + return 0; + lex(); + if (Token.isNot(MIToken::Eof)) + return error("expected end of string after the register reference"); + return false; +} + static const char *printImplicitRegisterFlag(const MachineOperand &MO) { assert(MO.isImplicit()); return MO.isDef() ? "implicit-def" : "implicit"; @@ -583,3 +596,11 @@ bool llvm::parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM, const SlotMapping &IRSlots, SMDiagnostic &Error) { return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseMBB(MBB); } + +bool llvm::parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM, + MachineFunction &MF, StringRef Src, + const PerFunctionMIParsingState &PFS, + const SlotMapping &IRSlots, + SMDiagnostic &Error) { + return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseNamedRegister(Reg); +} -- cgit v1.2.3