From 12045a4b59c1d0d72b687400b12b3d59a36393c3 Mon Sep 17 00:00:00 2001 From: Alex Lorenz Date: Mon, 27 Jul 2015 17:42:45 +0000 Subject: MIR Serialization: Serialize the machine function's liveins. Reviewers: Duncan P. N. Exon Smith llvm-svn: 243288 --- llvm/lib/CodeGen/MIRParser/MIParser.cpp | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'llvm/lib/CodeGen/MIRParser/MIParser.cpp') diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 656f2314315..bb25ec39eb0 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -98,6 +98,7 @@ public: bool parse(MachineInstr *&MI); bool parseMBB(MachineBasicBlock *&MBB); bool parseNamedRegister(unsigned &Reg); + bool parseStandaloneVirtualRegister(unsigned &Reg); bool parseRegister(unsigned &Reg); bool parseRegisterFlag(unsigned &Flags); @@ -289,6 +290,18 @@ bool MIParser::parseNamedRegister(unsigned &Reg) { return false; } +bool MIParser::parseStandaloneVirtualRegister(unsigned &Reg) { + lex(); + if (Token.isNot(MIToken::VirtualRegister)) + return error("expected a virtual register"); + if (parseRegister(Reg)) + return 0; + lex(); + if (Token.isNot(MIToken::Eof)) + return error("expected end of string after the register reference"); + return false; +} + static const char *printImplicitRegisterFlag(const MachineOperand &MO) { assert(MO.isImplicit()); return MO.isDef() ? "implicit-def" : "implicit"; @@ -843,3 +856,12 @@ bool llvm::parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM, SMDiagnostic &Error) { return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseNamedRegister(Reg); } + +bool llvm::parseVirtualRegisterReference(unsigned &Reg, SourceMgr &SM, + MachineFunction &MF, StringRef Src, + const PerFunctionMIParsingState &PFS, + const SlotMapping &IRSlots, + SMDiagnostic &Error) { + return MIParser(SM, MF, Error, Src, PFS, IRSlots) + .parseStandaloneVirtualRegister(Reg); +} -- cgit v1.2.3