From 7366fa1aa6d69a63e016abe7baec035690797f5a Mon Sep 17 00:00:00 2001 From: "Vikram S. Adve" Date: Tue, 27 May 2003 00:05:23 +0000 Subject: (1) Added special register class containing (for now) %fsr. Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. (3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly() and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". llvm-svn: 6341 --- llvm/lib/CodeGen/LiveVariables.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'llvm/lib/CodeGen/LiveVariables.cpp') diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp index 3d9758136ce..d38ed274e36 100644 --- a/llvm/lib/CodeGen/LiveVariables.cpp +++ b/llvm/lib/CodeGen/LiveVariables.cpp @@ -231,7 +231,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { // Process all explicit defs... for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.opIsDef() || MO.opIsDefAndUse()) { + if (MO.opIsDefOnly() || MO.opIsDefAndUse()) { if (MO.isVirtualRegister()) { VarInfo &VRInfo = getVarInfo(MO.getReg()); -- cgit v1.2.3