From 2182f06f2d839cfb3575a2004d066086829365c0 Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Fri, 13 Jul 2007 17:13:54 +0000 Subject: Skeleton of post-RA scheduler; doesn't do anything yet. Change name of -sched option and DEBUG_TYPE to pre-RA-sched; adjust testcases. llvm-svn: 39816 --- llvm/lib/CodeGen/LLVMTargetMachine.cpp | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'llvm/lib/CodeGen/LLVMTargetMachine.cpp') diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index 4e3982df62a..b50b2753922 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -78,6 +78,9 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); + // Second pass scheduler. + PM.add(createPostRAScheduler()); + // Branch folding must be run after regalloc and prolog/epilog insertion. if (!Fast) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); @@ -181,6 +184,9 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, if (PrintMachineCode) // Print the register-allocated code PM.add(createMachineFunctionPrinterPass(cerr)); + // Second pass scheduler. + PM.add(createPostRAScheduler()); + // Branch folding must be run after regalloc and prolog/epilog insertion. if (!Fast) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); -- cgit v1.2.3