From 98722691b0b5e375fdd02c9a464476752a3c598e Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Mon, 1 Jul 2019 08:21:28 +0000 Subject: [ARM] WLS/LE Code Generation Backend changes to enable WLS/LE low-overhead loops for armv8.1-m: 1) Use TTI to communicate to the HardwareLoop pass that we should try to generate intrinsics that guard the loop entry, as well as setting the loop trip count. 2) Lower the BRCOND that uses said intrinsic to an Arm specific node: ARMWLS. 3) ISelDAGToDAG the node to a new pseudo instruction: t2WhileLoopStart. 4) Add support in ArmLowOverheadLoops to handle the new pseudo instruction. Differential Revision: https://reviews.llvm.org/D63816 llvm-svn: 364733 --- llvm/lib/CodeGen/HardwareLoops.cpp | 1 + 1 file changed, 1 insertion(+) (limited to 'llvm/lib/CodeGen/HardwareLoops.cpp') diff --git a/llvm/lib/CodeGen/HardwareLoops.cpp b/llvm/lib/CodeGen/HardwareLoops.cpp index 0d754b902fa..5f57cabbe86 100644 --- a/llvm/lib/CodeGen/HardwareLoops.cpp +++ b/llvm/lib/CodeGen/HardwareLoops.cpp @@ -294,6 +294,7 @@ static bool CanGenerateTest(Loop *L, Value *Count) { // Check that the icmp is checking for equality of Count and zero and that // a non-zero value results in entering the loop. auto ICmp = cast(BI->getCondition()); + LLVM_DEBUG(dbgs() << " - Found condition: " << *ICmp << "\n"); if (!ICmp->isEquality()) return false; -- cgit v1.2.3