From 56606a4db3e7c6b4a1b3bfd3b2dfc04c81a2247e Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Wed, 21 Aug 2019 00:12:37 +0000 Subject: [AArch64][GlobalISel] Add support for narrowScalar of G_ZEXT We do this by merging the source with the high bits set to 0. Differential Revision: https://reviews.llvm.org/D66181 llvm-svn: 369480 --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp') diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index c5f23859783..26c25ba26d4 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -615,6 +615,24 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, MI.eraseFromParent(); return Legalized; } + case TargetOpcode::G_ZEXT: { + if (TypeIdx != 0) + return UnableToLegalize; + + if (SizeOp0 % NarrowTy.getSizeInBits() != 0) + return UnableToLegalize; + + // Generate a merge where the bottom bits are taken from the source, and + // zero everything else. + Register ZeroReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); + unsigned NumParts = SizeOp0 / NarrowTy.getSizeInBits(); + SmallVector Srcs = {MI.getOperand(1).getReg()}; + for (unsigned Part = 1; Part < NumParts; ++Part) + Srcs.push_back(ZeroReg); + MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs); + MI.eraseFromParent(); + return Legalized; + } case TargetOpcode::G_ADD: { // FIXME: add support for when SizeOp0 isn't an exact multiple of -- cgit v1.2.3