From 10ebfe0684ea6480a06638a6a2e1d23f50dacbff Mon Sep 17 00:00:00 2001 From: Andrew Ng Date: Tue, 25 Apr 2017 15:39:57 +0000 Subject: Resubmit r301309: [DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler. This patch reapplies r301309 with the fix to the MIR test to fix the assertion triggered by r301309. Had trimmed a little bit too much from the MIR! llvm-svn: 301317 --- llvm/lib/CodeGen/AntiDepBreaker.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'llvm/lib/CodeGen/AntiDepBreaker.h') diff --git a/llvm/lib/CodeGen/AntiDepBreaker.h b/llvm/lib/CodeGen/AntiDepBreaker.h index 04f7f419f5e..d14d93100ad 100644 --- a/llvm/lib/CodeGen/AntiDepBreaker.h +++ b/llvm/lib/CodeGen/AntiDepBreaker.h @@ -60,6 +60,25 @@ public: if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg) MI.getOperand(0).setReg(NewReg); } + + /// Update all DBG_VALUE instructions that may be affected by the dependency + /// breaker's update of ParentMI to use NewReg. + void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI, + unsigned OldReg, unsigned NewReg) { + // The following code is dependent on the order in which the DbgValues are + // constructed in ScheduleDAGInstrs::buildSchedGraph. + MachineInstr *PrevDbgMI = nullptr; + for (const auto &DV : make_range(DbgValues.crbegin(), DbgValues.crend())) { + MachineInstr *PrevMI = DV.second; + if ((PrevMI == ParentMI) || (PrevMI == PrevDbgMI)) { + MachineInstr *DbgMI = DV.first; + UpdateDbgValue(*DbgMI, OldReg, NewReg); + PrevDbgMI = DbgMI; + } else if (PrevDbgMI) { + break; // If no match and already found a DBG_VALUE, we're done. + } + } + } }; } -- cgit v1.2.3