From 96c81e9fff5cdaa880857d47d9fda85fb630523e Mon Sep 17 00:00:00 2001 From: "Vikram S. Adve" Date: Thu, 14 Aug 2003 20:45:56 +0000 Subject: Improvement to the previous fix: branch following a delay slot of another delayed instr. would cause the later sanity-check (assertion) in PhyRegAlloc.cpp to fail, even though there is really no error. llvm-svn: 7848 --- llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp') diff --git a/llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp b/llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp index 8cde6e1de7a..764ec36f37f 100644 --- a/llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp +++ b/llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp @@ -290,9 +290,11 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) { for (unsigned i = 0; i < DS; ++i, ++fwdMII) { assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?"); MachineInstr* DelaySlotMI = *fwdMII; - set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet); - if (i+1 == DS) - set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet); + if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpCode())) { + set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet); + if (i+1 == DS) + set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet); + } } } -- cgit v1.2.3