From 4f839ac1883afd6009f0062ccbcf85b799fd036b Mon Sep 17 00:00:00 2001 From: Strahinja Petrovic Date: Tue, 2 Apr 2019 11:00:09 +0000 Subject: [PowerPC] Fix issue with inline asm - soft float mode This patch prevents floating point register constraints in soft float mode. Differential Revision: https://reviews.llvm.org/D59310 llvm-svn: 357466 --- clang/lib/Basic/Targets/PPC.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'clang/lib/Basic/Targets/PPC.h') diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h index ace7eb35e76..7049020a911 100644 --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -53,6 +53,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { static const char *const GCCRegNames[]; static const TargetInfo::GCCRegAlias GCCRegAliases[]; std::string CPU; + enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; // Target cpu features. bool HasAltivec = false; @@ -183,8 +184,11 @@ public: return false; case 'O': // Zero break; - case 'b': // Base register case 'f': // Floating point register + // Don't use floating point registers on soft float ABI. + if (FloatABI == SoftFloat) + return false; + case 'b': // Base register Info.setAllowsRegister(); break; // FIXME: The following are added to allow parsing. @@ -192,6 +196,10 @@ public: // Also, is more specific checking needed? I.e. specific registers? case 'd': // Floating point register (containing 64-bit value) case 'v': // Altivec vector register + // Don't use floating point and altivec vector registers + // on soft float ABI + if (FloatABI == SoftFloat) + return false; Info.setAllowsRegister(); break; case 'w': -- cgit v1.2.3