From cac24ab04c34ff3e90269b732ad8e1cb049ae94e Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Mon, 17 Jul 2017 17:45:57 +0000 Subject: [SystemZ] Add support for IBM z14 processor (1/3) This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. Support for the -fzvector extension to vector float and the new high-level vector intrinsics is provided by separate patches. llvm-svn: 308197 --- clang/lib/Basic/Targets.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'clang/lib/Basic/Targets.cpp') diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index cac80b64b4f..cdd3a2d4b03 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -7503,6 +7503,7 @@ public: .Cases("arch9", "z196", 9) .Cases("arch10", "zEC12", 10) .Cases("arch11", "z13", 11) + .Cases("arch12", "z14", 12) .Default(-1); } bool setCPU(const std::string &Name) override { @@ -7519,6 +7520,8 @@ public: Features["transactional-execution"] = true; if (ISARevision >= 11) Features["vector"] = true; + if (ISARevision >= 12) + Features["vector-enhancements-1"] = true; return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); } @@ -7548,6 +7551,7 @@ public: .Case("arch9", ISARevision >= 9) .Case("arch10", ISARevision >= 10) .Case("arch11", ISARevision >= 11) + .Case("arch12", ISARevision >= 12) .Case("htm", HasTransactionalExecution) .Case("vx", HasVector) .Default(false); -- cgit v1.2.3