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* Removed trailing whitespace.Michael Gottesman2013-03-291-15/+15
| | | | llvm-svn: 178329
* [mips] Change type of accumulator registers to Untyped. Add two more accumulatorAkira Hatanaka2013-03-291-7/+30
| | | | | | | | register classes for Mips64 and DSP-ASE. No functionality changes. llvm-svn: 178328
* [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.Akira Hatanaka2013-03-295-43/+74
| | | | | | No functionality changes. llvm-svn: 178327
* [mips] Add parameter Alignment to MipsFrameLowering's constructor.Akira Hatanaka2013-03-293-5/+4
| | | | | | No functionality changes. llvm-svn: 178326
* Revert r178166. According to Howard, this code is actually ok.Dan Gohman2013-03-291-3/+1
| | | | llvm-svn: 178319
* [Mips Assembler] Add support for OR macro with imediate opperandJack Carter2013-03-283-1/+8
| | | | | | | | | Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic llvm-svn: 178316
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-2810-9/+203
| | | | llvm-svn: 178314
* Enhance boolean simplification to handle 16-/64-bit RDRANDMichael Liao2013-03-282-6/+43
| | | | | | | | | - RDRAND always clears the destination value when a random value is not available (i.e. CF == 0). This value is truncated or zero-extended as the false boolean value to be returned. Boolean simplification needs to skip this 'zext' or 'trunc' node. llvm-svn: 178312
* Skip moving call address loading into callseq when targets prefer register ↵Michael Liao2013-03-284-16/+7
| | | | | | | | | | | | | | | | | | indirect call. To enable a load of a call address to be folded with that call, this load is moved from outside of callseq into callseq. Such a moving adds a non-glued node (that load) into a glued sequence. This non-glue load is only removed when DAG selection folds them into a memory form call instruction. When such instruction selection is disabled, it breaks DAG schedule. To prevent that, such moving is disabled when target favors register indirect call. Previous workaround disabling CALL32m/CALL64m insn selection is removed. llvm-svn: 178308
* Removed dead code from ObjCARCOpts relating to tracking objc_retainBlocks ↵Michael Gottesman2013-03-281-37/+6
| | | | | | through the ARC Dataflow analysis. By the time we get to the ARC dataflow analysis, any objc_retainBlock calls are not optimizable. llvm-svn: 178306
* [fast-isel] Add a preemptive fix for the case where we fail to materialize anChad Rosier2013-03-281-0/+2
| | | | | | | | | | | immediate in a register. I don't believe this should ever fail, but I see no harm in trying to make this code bullet proof. I've added an assert to ensure my assumtion is correct. If the assertion fires something is wrong and we should fix it, rather then just silently fall back to SelectionDAG isel. llvm-svn: 178305
* [Mips Assembler] Add alias definitions for jalJack Carter2013-03-283-1/+22
| | | | | | | | | | | Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic llvm-svn: 178304
* Add the X86 FMAs to the scheduling model.Nadav Rotem2013-03-282-2/+6
| | | | llvm-svn: 178303
* Minor simplification.Bill Wendling2013-03-281-8/+4
| | | | | | Go ahead and use the full path for both the .gcno and .gcda files. llvm-svn: 178302
* Add the Haswell machine model.Nadav Rotem2013-03-283-1/+128
| | | | llvm-svn: 178301
* Remove the unused port from the SandyBridge machine modelNadav Rotem2013-03-281-1/+0
| | | | llvm-svn: 178300
* Add ADX CPUID detectionMichael Liao2013-03-281-0/+4
| | | | llvm-svn: 178299
* These two are default in the constructor for MCAsmInfo.Eric Christopher2013-03-281-2/+0
| | | | llvm-svn: 178293
* Make Win32 put the SRet address into EAX, fixes PR15556Timur Iskhodzhanov2013-03-283-20/+83
| | | | llvm-svn: 178291
* Specify CPUs on the PPC bswap-load-store testHal Finkel2013-03-281-2/+2
| | | | | | Otherwise, the CHECK-NOT's might trigger depending on the host's CPU. llvm-svn: 178287
* Only enable 64-bit bswap DAG combines for PPC64Hal Finkel2013-03-282-0/+3
| | | | | | | | Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were added for bswap with load/store. This is because these combines are really only valid in 64-bit mode, regardless of the CPU (and this was not being checked). llvm-svn: 178286
* Non optimizable objc_retainBlock calls are not forwarding.Michael Gottesman2013-03-282-5/+2
| | | | | | | | | | | | Since we handle optimizable objc_retainBlocks through strength reduction in OptimizableIndividualCalls, we know that all code after that point will only see non-optimizable objc_retainBlock calls. IsForwarding is only called by functions after that point, so it is ok to just classify objc_retainBlock as non-forwarding. <rdar://problem/13249661>. llvm-svn: 178285
* [ObjCARC] Strength reduce objc_retainBlock -> objc_retain if the ↵Michael Gottesman2013-03-283-15/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | objc_retainBlock is optimizable. If an objc_retainBlock has the copy_on_escape metadata attached to it AND if the block pointer argument only escapes down the stack, we are allowed to strength reduce the objc_retainBlock to to an objc_retain and thus optimize it. Current there is logic in the ARC data flow analysis to handle this case which is complicated and involved making distinctions in between objc_retainBlock and objc_retain in certain places and considering them the same in others. This patch simplifies said code by: 1. Performing the strength reduction in the initial ARC peephole analysis (ObjCARCOpts::OptimizeIndividualCalls). 2. Changes the ARC dataflow analysis (which runs after the peephole analysis) to consider all objc_retainBlock calls to not be optimizable (since if the call was optimizable, we would have strength reduced it already). This patch leaves in the infrastructure in the ARC dataflow analysis to handle this case, which due to 2 will just be dead code. I am doing this on purpose to separate the removal of the old code from the testing of the new code. <rdar://problem/13249661>. llvm-svn: 178284
* Hexagon: Replace switch-case in isDotNewInst with TSFlags.Jyotsna Verma2013-03-284-176/+26
| | | | llvm-svn: 178281
* Fix bad indentation in r178276Hal Finkel2013-03-281-2/+1
| | | | | | Thanks to Bill Schmidt for pointing this out! llvm-svn: 178280
* Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.Jyotsna Verma2013-03-282-1/+2
| | | | llvm-svn: 178279
* Remove -O3.Akira Hatanaka2013-03-281-3/+3
| | | | llvm-svn: 178278
* Use direct types in most PowerPC Altivec instructions and patterns.Bill Schmidt2013-03-281-236/+333
| | | | | | | | | | | | | | | | | | | | | | | This follows up Ulrich Weigand's work in PPCInstrInfo.td and PPCInstr64Bit.td by doing the corresponding work for most of the Altivec patterns. I have not been able to do anything for the following classes of instructions: (1) Vector logicals. These don't have corresponding intrinsics and don't have a single obvious vector type. So far as I can tell I need to leave these as VRRC. Affected instructions are: VAND, VANDC, VNOR, VOR, VXOR, V_SET0. (2) Instructions that make use of vector shuffle. The selection code promotes all shuffles to v16i8, so any pattern that matches on a shuffle is constrained. I haven't found any way to make the patterns match on their natural types, so I plan to leave these as VRRC. Affected instructions are: VMRG*, VSPLTB, VSPLTH, VSPLTW, VPKUHUM, VPKUWUM. No change in behavior is anticipated. llvm-svn: 178277
* Add the PPC64 ldbrx/stdbrx instructionsHal Finkel2013-03-287-20/+67
| | | | | | | | These are 64-bit load/store with byte-swap, and available on the P7 and the A2. Like the similar instructions for 16- and 32-bit words, these are matched in the target DAG-combine phase against load/store-bswap pairs. llvm-svn: 178276
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser2013-03-282-2/+5
| | | | | | | | the upper bit is set. They should always be zero-extended, not sign extended. Added test case. llvm-svn: 178275
* Testing commit access to llvm. Remove two lines of whitespace from the ↵Gordon Keiser2013-03-281-2/+0
| | | | | | Thumb README. llvm-svn: 178256
* Correct spelling of Git.Thomas Schwinge2013-03-282-6/+6
| | | | llvm-svn: 178254
* Move test since it depends on the X86 backend.Rafael Espindola2013-03-281-0/+0
| | | | llvm-svn: 178249
* Hexagon: Use multiclass for gp-relative instructions.Jyotsna Verma2013-03-283-1094/+237
| | | | | | Remove noV4T gp-relative instructions. llvm-svn: 178246
* Seciton 24.2.2 of the C++ standard, [iterator.iterators], Table 106Howard Hinnant2013-03-281-6/+10
| | | | | | | | | | | | | | | | | | | | | requires that the return type of *r for all iterators r be reference, where reference is defined in [iterator.requirements.general]/p11 as iterator_traits<X>::reference, and X is the type of r. But in CFG.h, the dereference operator of PredIterator and SuccIterator return pointer, not reference. Furthermore the nested type reference is value_type&, which is not the type returned from operator*(). This patch simply makes the iterator::reference type value_type*, which is what the operator*() returns, and then re-lables the return type as reference. From a functionality point of view, the only difference is that the nested reference type is now value_type* instead of value_type&. llvm-svn: 178240
* AArch64: implement GICv3 system registersTim Northover2013-03-285-5/+647
| | | | llvm-svn: 178236
* Add the PPC64 popcntd instructionHal Finkel2013-03-287-9/+64
| | | | | | | PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and tell TTI about it so that popcount-loop recognition will know about it. llvm-svn: 178233
* [tsan] make sure memset/memcpy/memmove are not inlined in tsan modeKostya Serebryany2013-03-282-0/+85
| | | | llvm-svn: 178230
* Revert "Updated ELF relocation test for .eh_frame section"Michael Gottesman2013-03-282-83/+4
| | | | | | | | This reverts commit c8d65364223a04b179958a50a4bf0f89b21dd7d2. This broke a bunch of the buildbots. llvm-svn: 178222
* Disable JIT/MCJIT tests in unittests/ExecutionEngine for the targets that ↵Jyotsna Verma2013-03-282-3/+10
| | | | | | don't support JIT. llvm-svn: 178221
* Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructionsHal Finkel2013-03-284-12/+420
| | | | | | | | There were a few places where kill flags were not being set correctly, and where 32-bit instruction variants were being used with 64-bit registers. After r178180, this code was being triggered causing llc to assert. llvm-svn: 178220
* Fix typo in PPCInstr64BitHal Finkel2013-03-281-1/+1
| | | | llvm-svn: 178219
* Revert "Adding DIImportedModules to DIScopes."David Blaikie2013-03-2899-1473/+1354
| | | | | | | | | This reverts commit 342d92c7a0adeabc9ab00f3f0d88d739fe7da4c7. Turns out we're going with a different schema design to represent DW_TAG_imported_modules so we won't need this extra field. llvm-svn: 178215
* Check if Type is a vector before calling function Type::getVectorNumElements.Akira Hatanaka2013-03-282-3/+19
| | | | llvm-svn: 178208
* This patch follows is a follow up to r178171, which uses the register Preston Gurd2013-03-275-5/+431
| | | | | | | | | | | | | | form of call in preference to memory indirect on Atom. In this case, the patch applies the optimization to the code for reloading spilled registers. The patch also includes changes to sibcall.ll and movgs.ll, which were failing on the Atom buildbot after the first patch was applied. This patch by Sriram Murali. llvm-svn: 178193
* Updated ELF relocation test for .eh_frame sectionJack Carter2013-03-272-4/+83
| | | | | | | | Made sure we were looking a correct section Added Mips32/64 as an extra check Updated llvm-objdump to generate symbolic info for Mips relocations llvm-svn: 178190
* [ms-inline asm] Add support of imm displacement before bracketed memoryChad Rosier2013-03-272-15/+72
| | | | | | | | | | | | | | expression. Specifically, this syntax: ImmDisp [ BaseReg + Scale*IndexReg + Disp ] We don't currently support: ImmDisp [ Symbol ] rdar://13518671 llvm-svn: 178186
* Resynchronize isLoadFromStackSlot with LoadRegFromStackSlot (and stores) in ↵Hal Finkel2013-03-271-0/+18
| | | | | | | | | | | | | PPCInstrInfo These functions should have the same list of load/store instructions. Now that all load/store forms have been normalized (to single instructions or pseudos) they can be resynchronized. Found by inspection, although hopefully this will improve optimization. I've also added some comments. llvm-svn: 178180
* test file name change to correct typoJack Carter2013-03-271-0/+0
| | | | llvm-svn: 178174
* For the current Atom processor, the fastest way to handle a callPreston Gurd2013-03-275-1/+70
| | | | | | | | | | | | | indirect through a memory address is to load the memory address into a register and then call indirect through the register. This patch implements this improvement by modifying SelectionDAG to force a function address which is a memory reference to be loaded into a virtual register. Patch by Sriram Murali. llvm-svn: 178171
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