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* [PM] Flesh out almost all of the late loop passes.Chandler Carruth2017-01-272-9/+43
| | | | | | | | | | | | | | | | | | | | | | | | | With this the per-module pass pipeline is *extremely* close to the legacy PM. The missing pieces are: - PruneEH (or some equivalent) - ArgumentPromotion - LoopLoadElimination - LoopUnswitch I'm going to work through those in essentially that order but this seems like a worthwhile incremental step toward the end state. One difference in what I have here from the legacy PM is that I've consolidated some of the per-function passes at the very end of the pipeline into the main optimization function pipeline. The intervening passes are *really* uninteresting and so this seems very likely to have any effect other than minor improvement to locality. Note that there are still some failures in the test suite, but the compiler doesn't crash or assert. Differential Revision: https://reviews.llvm.org/D29114 llvm-svn: 293241
* [libFuzzer] simplify the value profiling callback further: don't use (idx ↵Kostya Serebryany2017-01-273-10/+11
| | | | | | MOD prime) on the hot path where it is useless anyway llvm-svn: 293239
* [AArch64][LegalizerInfo] Specify the type of the initialization list.Quentin Colombet2017-01-271-70/+76
| | | | | | | This is an attempt to fix the win7 bot that does not seem to be very good at infering the type. llvm-svn: 293238
* [libFuzzer] make sure (again) that __builtin_popcountl is compiled into popcntKostya Serebryany2017-01-271-0/+8
| | | | llvm-svn: 293237
* [libFuzzer] simplify the value profile code and disable asan/msan on itKostya Serebryany2017-01-273-6/+19
| | | | llvm-svn: 293236
* NFC: Rename PDB_ReaderType::Raw to Native for consistency with the ↵Adrian McCarthy2017-01-273-6/+6
| | | | | | NativeSession rename. llvm-svn: 293235
* Switch the default for building GlobalISel.Quentin Colombet2017-01-261-1/+1
| | | | | | | | | Now, GlobalISel will be built by default. To turn that off, one has to use -DLLVM_BUILD_GLOBAL_ISEL=OFF on the cmake command line. <rdar://problem/30004433> llvm-svn: 293232
* CMake is funky on detecting Intel 17 as GCC compatible.Yichao Yu2017-01-261-0/+2
| | | | | | | | | | | | | | Summary: This adds a fallback in case that the Intel compiler is failed to be detected correctly. Reviewers: chapuni Reviewed By: chapuni Subscribers: llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D27610 llvm-svn: 293230
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-01-2613-131/+244
| | | | | | minor fixes (NFC). llvm-svn: 293229
* GlobalISel: support debug intrinsics.Tim Northover2017-01-265-38/+192
| | | | | | | | The translation scheme is mostly cribbed from FastISel, and it's not entirely convincing semantically. But it does seem to work in the common cases and allow variables to be printed so it can't be all wrong. llvm-svn: 293228
* Revert a couple of InstCombine/Guard checkinsSanjoy Das2017-01-262-75/+0
| | | | | | | | | | | | | | | | | | | | | | | | | This change reverts: r293061: "[InstCombine] Canonicalize guards for NOT OR condition" r293058: "[InstCombine] Canonicalize guards for AND condition" They miscompile cases like: ``` declare void @llvm.experimental.guard(i1, ...) define void @test_guard_not_or(i1 %A, i1 %B) { %C = or i1 %A, %B %D = xor i1 %C, true call void(i1, ...) @llvm.experimental.guard(i1 %D, i32 20, i32 30)[ "deopt"() ] ret void } ``` because they do transfer the `i32 20, i32 30` parameters to newly created guard instructions. llvm-svn: 293227
* Add intrinsics for constrained floating point operationsAndrew Kaylor2017-01-2613-0/+768
| | | | | | | | | | | | | | This commit introduces a set of experimental intrinsics intended to prevent optimizations that make assumptions about the rounding mode and floating point exception behavior. These intrinsics will later be extended to specify flush-to-zero behavior. More work is also required to model instruction dependencies in machine code and to generate these instructions from clang (when required by pragmas and/or command line options that are not currently supported). Differential Revision: https://reviews.llvm.org/D27028 llvm-svn: 293226
* [PM] Enable the main loop pass pipelines with everything butChandler Carruth2017-01-262-12/+14
| | | | | | | | | | | | | | | | loop-unswitch in the main pipelines for the new PM. All of these now work, and Clang built using this pipeline can build the test suite and SPEC without hitting any asserts of ASan failures. There are still some bugs hiding though -- 7 tests regress with the new PM. I'm going to be investigating these, but it seems worthwhile to at least get the pipelines in place so that others can play with them, and they aren't completely broken. Differential Revision: https://reviews.llvm.org/D29113 llvm-svn: 293225
* [obj2yaml] Produce correct output for invalid relocations.Davide Italiano2017-01-263-4/+49
| | | | | | | | | | | | R_X86_64_NONE can be emitted without a symbol associated (well, in theory it should never be emitted in an ABI-compliant relocatable object). So, if there's no symbol associated to a reloc, emit one with an empty name, instead of crashing. Ack'ed by Michael Spencer offline. PR: 31768 llvm-svn: 293224
* [Hexagon] Require IPO library in Hexagon buildKrzysztof Parzyszek2017-01-261-0/+1
| | | | | | This should unbreak the Hexagon build bots. llvm-svn: 293221
* NewGVN: Fix bug exposed by PR31761Daniel Berlin2017-01-262-46/+87
| | | | | | | | | | | | | | | | | | | Summary: This does not actually fix the testcase in PR31761 (discussion is ongoing on the testcase), but does fix a bug it exposes, where stores were not properly clobbering loads. We accomplish this by unifying the memory equivalence infratructure back into the normal congruence infrastructure, and then properly destroying congruence classes when memory state leaders disappear. Reviewers: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29195 llvm-svn: 293216
* [InstCombine] fold (X >>u C) << C --> X & (-1 << C)Sanjay Patel2017-01-262-22/+21
| | | | | | | | | | | | | | | We already have this fold when the lshr has one use, but it doesn't need that restriction. We may be able to remove some code from foldShiftedShift(). Also, move the similar: (X << C) >>u C --> X & (-1 >>u C) ...directly into visitLShr to help clean up foldShiftByConstOfShiftByConst(). That whole function seems questionable since it is called by commonShiftTransforms(), but there's really not much in common if we're checking the shift opcodes for every fold. llvm-svn: 293215
* [GlobalISel] Remove duplicate function using variadic templates. NFC.Ahmed Bougacha2017-01-261-21/+5
| | | | | | | | | I think the initial version of r293172 was trying: std::forward<Args...>(args)... which doesn't compile. This seems like the correct way: std::forward<Args>(args)... llvm-svn: 293214
* [Hexagon] Add Hexagon-specific loop idiom recognition passKrzysztof Parzyszek2017-01-269-5/+1812
| | | | llvm-svn: 293213
* NewGVN: Add algorithm overviewDaniel Berlin2017-01-261-0/+21
| | | | llvm-svn: 293212
* [InstCombine] use m_APInt to allow (X << C) >>u C --> X & (-1 >>u C) with ↵Sanjay Patel2017-01-262-18/+26
| | | | | | splat vectors llvm-svn: 293208
* [Doc][LangRef] Fix typo-ish error in description of Masked GatherZvi Rackover2017-01-261-1/+1
| | | | | | | | | | | | | | Summary: Fix the example of equivalent expansion for when mask is all ones. Reviewers: delena Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29179 llvm-svn: 293206
* [InstCombine] add tests for shift-shift folds; NFCSanjay Patel2017-01-261-0/+60
| | | | llvm-svn: 293205
* [AArch64] Refine Kryo Machine ModelBalaram Makam2017-01-261-22/+40
| | | | | | | | | | | | Summary: Refine floating point SQRT and DIV with accurate latency information. Reviewers: mcrosier Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D29191 llvm-svn: 293204
* [IfConversion] Use reverse_iterator to simplify. NFCKyle Butt2017-01-261-70/+35
| | | | | | This simplifies skipping debug instructions and shrinking ranges. llvm-svn: 293202
* [PPC] cleanup of mayLoad/mayStore flags and memory operands.Sean Fertile2017-01-267-44/+46
| | | | | | | | | | | | 1) Explicitly sets mayLoad/mayStore property in the tablegen files on load/store instructions. 2) Updated the flags on a number of intrinsics indicating that they write memory. 3) Added SDNPMemOperand flags for some target dependent SDNodes so that they propagate their memory operand Review: https://reviews.llvm.org/D28818 llvm-svn: 293200
* NewGVN: Fix output of pr31578 testcase now that we mark unreachable blocks ↵Daniel Berlin2017-01-261-13/+12
| | | | | | as unreachable llvm-svn: 293198
* NewGVN: Make unreachable blocks be marked with unreachableDaniel Berlin2017-01-263-38/+33
| | | | llvm-svn: 293196
* Replace addEarlyAsPossiblePasses callback with adjustPassManagerStanislav Mekhanoshin2017-01-266-17/+24
| | | | | | | | | | | | | | This change introduces adjustPassManager target callback giving a target an opportunity to tweak PassManagerBuilder before pass managers are populated. This generalizes and replaces addEarlyAsPossiblePasses target callback. In particular that can be used to add custom passes to extension points other than EP_EarlyAsPossible. Differential Revision: https://reviews.llvm.org/D28336 llvm-svn: 293189
* Revert "In visitSTORE, always use FindBetterChain, rather than only when ↵Nirav Dave2017-01-2671-2050/+2207
| | | | | | | | UseAA is enabled." This reverts commit r293184 which is failing in LTO builds llvm-svn: 293188
* [XRay][Arm32] Reduce the portion of the stub and implement more staging for ↵Serge Rogatch2017-01-262-0/+15
| | | | | | | | | | | | | | | | | | | tail calls - in LLVM Summary: This patch provides more staging for tail calls in XRay Arm32 . When the logging part of XRay is ready for tail calls, its support in the core part of XRay Arm32 may be as easy as changing the number passed to the handler from 1 to 2. Coupled patch: - https://reviews.llvm.org/D28674 Reviewers: dberris, rengolin Reviewed By: dberris Subscribers: llvm-commits, iid_iunknown, aemerson, rengolin, dberris Differential Revision: https://reviews.llvm.org/D28673 llvm-svn: 293185
* In visitSTORE, always use FindBetterChain, rather than only when UseAA is ↵Nirav Dave2017-01-2671-2207/+2050
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enabled. * Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search and chain alias analysis which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. When merging stores search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and the output Codegen (save perhaps for some ARM cases where we correctly constructs wider loads, but then promotes them to float operations which appear but requires more expensive constant generation). Some minor peephole optimizations to deal with improved SubDAG shapes (listed below) Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seems sufficient to not cause regressions in tests. 5. Remove Chain dependencies of Memory operations on CopyfromReg nodes as these are captured by data dependence 6. Forward loads-store values through tokenfactors containing {CopyToReg,CopyFromReg} Values. 7. Peephole to convert buildvector of extract_vector_elt to extract_subvector if possible (see CodeGen/AArch64/store-merge.ll) 8. Store merging for the ARM target is restricted to 32-bit as some in some contexts invalid 64-bit operations are being generated. This can be removed once appropriate checks are added. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable, improving load-store forwarding. One test in particular is worth noting: CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store forwarding converts a load-store pair into a parallel store and a memory-realized bitcast of the same value. However, because we lose the sharing of the explicit and implicit store values we must create another local store. A similar transformation happens before SelectionDAG as well. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle llvm-svn: 293184
* Use shouldAssumeDSOLocal in classifyGlobalReference.Rafael Espindola2017-01-264-25/+13
| | | | | | | | | | And teach shouldAssumeDSOLocal that ppc has no copy relocations. The resulting code handle a few more case than before. For example, it knows that a weak symbol can be resolved to another .o file, but it will still be in the main executable. llvm-svn: 293180
* [X86][SSE] Add support for combining ANDNP byte masks with target shufflesSimon Pilgrim2017-01-262-39/+47
| | | | llvm-svn: 293178
* [SCEV] Introduce add operation inlining limitDaniil Fukalov2017-01-262-0/+25
| | | | | | | | | | | | | Inlining in getAddExpr() can cause abnormal computational time in some cases. New parameter -scev-addops-inline-threshold is intruduced with default value 500. Reviewers: sanjoy Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D28812 llvm-svn: 293176
* [X86][SSE] Pull out target shuffle resolve code into helper. NFCI.Simon Pilgrim2017-01-261-14/+21
| | | | | | Pulled out code that removed unused inputs from a target shuffle mask into a helper function to allow it to be reused in a future commit. llvm-svn: 293175
* Remove a '#if 0' that wasn't intended for commit in r293173.Daniel Sanders2017-01-261-19/+0
| | | | | | | The '#if 0' contained the code I had intended to use but clang rejects it (possibly incorrectly). llvm-svn: 293174
* Attempt to fix windows buildbots after r293172.Daniel Sanders2017-01-261-1/+1
| | | | llvm-svn: 293173
* [globalisel] Re-factor ISel matchers into a hierarchy. NFCDaniel Sanders2017-01-261-48/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This should make it possible to easily add everything needed to import all the existing SelectionDAG rules. It should also serve the likely kinds of GlobalISel rules (some of which are not currently representable in SelectionDAG) once we've nailed down the tablegen definition for that. The hierarchy is as follows: MatcherRule - A matching rule. Currently used to emit C++ ISel code but will | also be used to emit test cases and tablegen definitions in the | near future. |- Instruction(s) - Represents the instruction to be matched. |- Instruction Predicate(s) - Test the opcode, arithmetic flags, etc. of an | instruction. \- Operand(s) - Represents a particular operand of the instruction. In the | future, there may be subclasses to test the same predicates | on multiple operands (including for variadic instructions). \ Operand Predicate(s) - Test the type, register bank, etc. of an operand. This is where the ComplexPattern equivalent will be represented. It's also nested-instruction matching will live as a predicate that follows the DefUse chain to the Def and tests a MatcherRule from that position. Support for multiple instruction matchers in a rule has been retained from the existing code but has been adjusted to assert when it is used. Previously it would silently drop all but the first instruction matcher. The tablegen-erated file is not functionally changed but has more parentheses and no longer attempts to format the if-statements since keeping track of the indentation is tricky in the presence of the matcher hierarchy. It would be nice to have CMakes tablegen() run the output through clang-format (when available) so we don't have to complicate TableGen with pretty-printing. It's also worth mentioning that this hierarchy will also be able to emit TableGen definitions and test cases in the near future. This is the reason for favouring explicit emit*() calls rather than the << operator. Reviewers: aditya_nandakumar, rovka, t.p.northover, qcolombet, ab Reviewed By: ab Subscribers: igorb, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D28942 llvm-svn: 293172
* [AMDGPU] Fix typo in GCNSchedStrategyValery Pykhtin2017-01-262-9/+4
| | | | | | Differential revision: https://reviews.llvm.org/D28980 llvm-svn: 293171
* Revert "[mips] N64 static relocation model support"Simon Dardis2017-01-2650-613/+352
| | | | | | This reverts commit r293164. There are multiple tests failing. llvm-svn: 293170
* [LV] Fix an issue where forming LCSSA in the place that we did wouldChandler Carruth2017-01-262-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | change the set of uniform instructions in the loop causing an assert failure. The problem is that the legalization checking also builds data structures mapping various facts about the loop body. The immediate cause was the set of uniform instructions. If these then change when LCSSA is formed, the data structures would already have been built and become stale. The included test case triggered an assert in loop vectorize that was reduced out of the new PM's pipeline. The solution is to form LCSSA early enough that no information is cached across the changes made. The only really obvious position is outside of the main logic to vectorize the loop. This also has the advantage of removing one case where forming LCSSA could mutate the loop but we wouldn't track that as a "Changed" state. If it is significantly advantageous to do some legalization checking prior to this, we can do a more careful positioning but it seemed best to just back off to a safe position first. llvm-svn: 293168
* [mips] N64 static relocation model supportSimon Dardis2017-01-2650-352/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293164
* [ARM] GlobalISel: Load i1, i8 and i16 args from stackDiana Picus2017-01-266-22/+128
| | | | | | | | | | | | | Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
* [SLP] Add one more reduction operation for extra argument test to makeAlexey Bataev2017-01-261-2/+8
| | | | | | it vectorizable. llvm-svn: 293162
* [PM] Use PoisoningVH correctly when merely deleting entries in a mapChandler Carruth2017-01-261-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | with it. This code was dereferencing the PoisoningVH which isn't allowed once it is poisoned. But the code itself really doesn't need to access the pointer, it is just doing the safe stuff of clearing out data structures keyed on the pointer value. Change the code to use iterators to erase directly from a DenseMap. This is also substantially more efficient as it avoids lots of hashing and lookups to do the erasure. DenseMap supports iterating behind the iteration which is fairly easy to implement. Sadly, I don't have a test case here. I'm not even close and I don't know that I ever will be. The issue is that several of the tricky aspects of fixing this only show up when you cause the stack's SmallVector to be in *EXACTLY* the right location. I only ever got a reproduction for those with Clang, and only with *exactly* the right command line flags. Any adjustment, even to seemingly unrelated flags, would make partial and half-way solutions magically start to "work". In good news, all of this was caught with the LLVM test suite. Also, there is no *specific* code here that is untested, just that the old pattern of code won't immediately fail on any test case I've managed to contrive. llvm-svn: 293160
* Chapter3/KaleidoscopeJIT.h: Fix a warning. [-Wunused-lambda-capture]NAKAMURA Takumi2017-01-261-1/+1
| | | | | | "this", aka class members, is not referred in the body. llvm-svn: 293159
* [TargetTransformInfo] Add override keywords to supporess ↵Craig Topper2017-01-261-2/+3
| | | | | | -Winconsistent-missing-override. llvm-svn: 293158
* [AVX-512] Move the combine that runs combineBitcastForMaskedOp to the last ↵Craig Topper2017-01-261-1/+1
| | | | | | DAG combine phase where I had originally meant to put it. llvm-svn: 293157
* [X86] When bitcasting INSERT_SUBVECTOR/EXTRACT_SUBVECTOR to match masked ↵Craig Topper2017-01-261-2/+2
| | | | | | operations, use the correct type for the immediate operand. llvm-svn: 293156
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