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* Sphinxify the CMake document.Bill Wendling2012-07-063-585/+425
| | | | llvm-svn: 159806
* [arm-fast-isel] Add support for vararg function calls.Jush Lu2012-07-062-26/+76
| | | | llvm-svn: 159804
* Changes per review of commit 159787Jack Carter2012-07-061-6/+5
| | | | | | | | | | Mips specific inline asm operand modifier D. Comment changes and predicate change. llvm-svn: 159802
* Untabify and move a function near similar functions dealing with structEric Christopher2012-07-061-29/+30
| | | | | | types. llvm-svn: 159801
* Add some comments suggested in code review.Jakob Stoklund Olesen2012-07-061-0/+7
| | | | llvm-svn: 159800
* Enable new[] on llvm::BumpPtrAllocator.Dmitri Gribenko2012-07-061-0/+17
| | | | llvm-svn: 159789
* Mips specific inline asm operand modifier D.Jack Carter2012-07-052-29/+94
| | | | | | | | | | | | Print the second half of a double word operand. The include list was cleaned up a bit as well. Also the test case was modified to test for both big and little patterns. llvm-svn: 159787
* Fix an overzealous assertion. It is legitimate for a target to have ↵Owen Anderson2012-07-051-1/+1
| | | | | | multiple fixups on a single instruction that target the same byte, so long as their bit-offsets are coordinates appropriately. llvm-svn: 159785
* test case for r159770.Akira Hatanaka2012-07-051-0/+15
| | | | llvm-svn: 159771
* Enclose instruction rdhwr with directives, which are needed when target isAkira Hatanaka2012-07-051-0/+18
| | | | | | mips32 rev1 (the directives are emitted when target is mips32r2 too). llvm-svn: 159770
* Enable target dependent directive parsing to hook before standard parser inAkira Hatanaka2012-07-051-3/+5
| | | | | | | | AsmParser::ParseStatement. Patch by Vladimir Medic. llvm-svn: 159768
* add @llvm.donothingNuno Lopes2012-07-051-2/+28
| | | | llvm-svn: 159758
* Optimize extendIntervalEndTo a tiny bit by saving one call through theChandler Carruth2012-07-051-7/+7
| | | | | | vector erase. No functionality changed. llvm-svn: 159746
* Remove dead infrastructure for building DenseMaps with a SlotIndex asChandler Carruth2012-07-051-31/+0
| | | | | | | | the key -- they are now stored in an IntervalMap. I noticed this while looking into PR12652. llvm-svn: 159745
* Finish fixing the MachineOperand hashing, providing a nice modernChandler Carruth2012-07-052-47/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | hash_value overload for MachineOperands. This addresses a FIXME sufficient for me to remove it, and cleans up the code nicely too. The important changes to the hashing logic: - TargetFlags are now included in all of the hashes. These were complete missed. - Register operands have their subregisters and whether they are a def included in the hash. - We now actually hash all of the operand types. Previously, many operand types were simply *dropped on the floor*. For example: - Floating point immediates - Large integer immediates (>64-bit) - External globals! - Register masks - Metadata operands - It removes the offset from the block-address hash; I'm a bit suspicious of this, but isIdenticalTo doesn't consider the offset for black addresses. Any patterns involving these entities could have triggered extreme slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs you think might be closed now... I'm looking myself, but I may miss them. llvm-svn: 159743
* All cases are covered, no need for a default. This deals with theDuncan Sands2012-07-051-1/+0
| | | | | | corresponding clang warning. llvm-svn: 159742
* The hash function for MI expressions, used by MachineCSE, is reallyChandler Carruth2012-07-051-3/+8
| | | | | | | | | | | | | | | | | | | | | broken. This patch fixes the superficial problems which lead to the intractably slow compile times reported in PR13225. The specific issue is that we were failing to include the *offset* of a global variable in the hash code. Oops. This would in turn cause all MIs which were only distinguishable due to operating on different offsets of a global variable to produce identical hash functions. In some of the test cases attached to the PR I saw hash table activity where there were O(1000) probes-per-lookup *on average*. A very few entries were responsible for most of these probes. There is still quite a bit more to do here. The ad-hoc layering of data in MachineOperands makes them *extremely* brittle to hash correctly. We're missing quite a few other cases, the only ones I've fixed here are the specific MO types which were allowed through the assert() in getOffset(). llvm-svn: 159741
* Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1Duncan Sands2012-07-052-9/+72
| | | | | | booleans. Patch by James Benton. llvm-svn: 159739
* [tsan] fix compile-time falilure found while building Chromium with tsan ↵Kostya Serebryany2012-07-051-0/+5
| | | | | | (tsan issue #3). A unit test will follow separately. llvm-svn: 159736
* Remove ParentMap. You can just ask the domnode for its parent. No functionalityNick Lewycky2012-07-051-11/+8
| | | | | | | | | | change. Move the "Not profitable, avoid CSE!" debug message next to where we fail the check for profitability and use a different message for avoiding CSE due to being in different register classes. llvm-svn: 159729
* Make X86 call and return instructions non-variadic.Jakob Stoklund Olesen2012-07-044-34/+34
| | | | | | | Function argument and return value registers aren't part of the encoding, so they should be implicit operands. llvm-svn: 159728
* Allow trailing physreg RegisterSDNode operands on non-variadic instructions.Jakob Stoklund Olesen2012-07-043-14/+30
| | | | | | | | | | | | | | | Also allow trailing register mask operands on non-variadic both MachineSDNodes and MachineInstrs. The extra physreg RegisterSDNode operands are added to the MI as <imp-use> operands. This makes it possible to have non-variadic call instructions. Call and return instructions really are non-variadic, the argument registers should only be used implicitly - they are not part of the encoding. llvm-svn: 159727
* Print SlotIndexes when available for -print-machineinstrs.Jakob Stoklund Olesen2012-07-041-1/+2
| | | | llvm-svn: 159726
* Allow multiple terminators to read virtual registers.Jakob Stoklund Olesen2012-07-041-33/+29
| | | | | | | | Find the kill as the last terminator to read SrcReg. Patch by Philipp Brüschweiler! llvm-svn: 159722
* Ensure CopyToReg nodes are always glued to the call instruction.Jakob Stoklund Olesen2012-07-043-44/+34
| | | | | | | | | | | | | The CopyToReg nodes that set up the argument registers before a call must be glued to the call instruction. Otherwise, the scheduler may emit the physreg copies long before the call, causing long live ranges for the fixed registers. Besides disabling good register allocation, that can also expose problems when EmitInstrWithCustomInserter() splits a basic block during the live range of a physreg. llvm-svn: 159721
* Make sure -print-machineinstrs applies to the first pass as well.Jakob Stoklund Olesen2012-07-041-3/+3
| | | | llvm-svn: 159720
* Add a testcase for pr13209. It is not a great test, but it still fails ifRafael Espindola2012-07-041-0/+74
| | | | | | | 159509 and 159479 are reverted. It would be really nice to be able to run just the coalescer :-( llvm-svn: 159715
* Fix a bug in DebugInfo lib, extend a comment for one of the methodsAlexey Samsonov2012-07-042-3/+3
| | | | llvm-svn: 159707
* Reverted r159658:Stepan Dyatkovskiy2012-07-041-84/+2
| | | | | | Optimized diff operation: implemented the case when LHS and RHS subsets contains single numbers only. llvm-svn: 159704
* Reverted r156659, due to probable performance regressions, DenseMap should ↵Stepan Dyatkovskiy2012-07-043-17/+41
| | | | | | | | | | be used here: IntegersSubsetMapping - Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement if possible. llvm-svn: 159703
* Reduce some code duplication.Eric Christopher2012-07-041-19/+4
| | | | llvm-svn: 159701
* Fix some ascii art in a comment to not have trailing backslashes (inspirationMatt Beaumont-Gay2012-07-041-5/+5
| | | | | | | from IfConversion.cc), and fix some spelling and grammar in the surrounding prose. llvm-svn: 159699
* Add early if-conversion support to X86.Jakob Stoklund Olesen2012-07-044-1/+133
| | | | | | | | | Implement the TII hooks needed by EarlyIfConversion to create cmov instructions and estimate their latency. Early if-conversion is still not enabled by default. llvm-svn: 159695
* Add an experimental early if-conversion pass, off by default.Jakob Stoklund Olesen2012-07-047-0/+649
| | | | | | | | | | | | | This pass performs if-conversion on SSA form machine code by speculatively executing both sides of the branch and using a cmov instruction to select the result. This can help lower the number of branch mispredictions on architectures like x86 that don't have predicable instructions. The current implementation is very aggressive, and causes regressions on mosts tests. It needs good heuristics that have yet to be implemented. llvm-svn: 159694
* PHINode::hasConstantValue(): return undef if the PHI is fully recursive.Nuno Lopes2012-07-032-1/+3
| | | | | | Thanks Duncan for the idea llvm-svn: 159687
* Use the DebugInfo's 'print()' method to emit the comments.Bill Wendling2012-07-031-3/+5
| | | | | | | These give quite a bit more information about the DebugInfo and makes it more readable. llvm-svn: 159680
* BoundsChecking: optimize out the check for offset < 0 if size is known to ↵Nuno Lopes2012-07-032-9/+16
| | | | | | | | be >= 0 (signed). (LLVM optimizers cannot do this optimization by themselves) llvm-svn: 159668
* fold PHI nodes in SizeOffsetEvaluator whenever possible.Nuno Lopes2012-07-032-6/+20
| | | | | | Unfortunately this change requires the cache map to hold WeakVHs instead llvm-svn: 159667
* improve PHINode::hasConstantValue() to detect recursive cases like %phi = ↵Nuno Lopes2012-07-031-2/+6
| | | | | | phi(%phi,42) as constant llvm-svn: 159666
* IntegersSubsetMappin: cosmetic changes in diff operation.Stepan Dyatkovskiy2012-07-031-6/+6
| | | | llvm-svn: 159661
* Part of r159527. Splitted into series of patches and gone with fixed PR13256:Stepan Dyatkovskiy2012-07-031-1/+96
| | | | | | | | | | | | | | | IntegersSubsetMapping Added new methods - add(self& RHS, SuccessorClass *S) - detachCase - removeCase - findSuccessor - getCases - getCaseSingleNumber - isOverlapped llvm-svn: 159660
* Part of r159527. Splitted into series of patches and gone with fixed PR13256:Stepan Dyatkovskiy2012-07-033-42/+18
| | | | | | | | IntegersSubsetMapping - Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement if possible. llvm-svn: 159659
* Part of r159527. Splitted into series of patches and gone with fixed PR13256:Stepan Dyatkovskiy2012-07-031-2/+84
| | | | | | Optimized diff operation: implemented the case when LHS and RHS subsets contains single numbers only. llvm-svn: 159658
* Document the llvm.fabs intrinsic.Peter Collingbourne2012-07-031-0/+35
| | | | llvm-svn: 159657
* Micro-optimize this function a bit. This shrinks the generated codeChandler Carruth2012-07-031-4/+6
| | | | | | | | | some, and allows the routine to be inlined into common callers. The various bits that hit this code in their hotpath seem slightly lower on the profile, but I can't really measure a performance improvement as everything seems to still be bottlenecked on likely cache misses. =/ llvm-svn: 159648
* Remove extra space.Craig Topper2012-07-031-12/+12
| | | | llvm-svn: 159647
* Change i128mem/i256mem to f128mem/f256mem on some floating point vector ↵Craig Topper2012-07-031-14/+14
| | | | | | instructions. llvm-svn: 159646
* MCContext.cpp: Fixup for my odd previous commit. No functional changes.NAKAMURA Takumi2012-07-031-1/+1
| | | | llvm-svn: 159645
* Add aliases for pblendvb, blendvpd, and blendvps instructions with the ↵Craig Topper2012-07-032-5/+45
| | | | | | implicit xmm0 operand specified. Fixes PR13252. llvm-svn: 159644
* test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines.NAKAMURA Takumi2012-07-031-4/+0
| | | | llvm-svn: 159643
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