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* Update to not depend on "llvm-objdump -d -symbolize".Rafael Espindola2014-09-031-4/+10
| | | | llvm-svn: 217047
* R600/SI: Add a pattern for i64 and in a branchTom Stellard2014-09-032-0/+21
| | | | llvm-svn: 217041
* R600/SI: Fix typos in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-09-031-2/+2
| | | | | | | | | | This fixes a crash in the OpenCV test: ImgprocWarpResizeArea/Resize.Mat/16 There is no test case for this, because this failure depends on a specific ordering of the loads, which could easily change. llvm-svn: 217040
* Check-label a bit more specificRenato Golin2014-09-031-1/+1
| | | | | | Sometimes, the .file could be reordered and it'd identify the ldr in the filename as a bad match. llvm-svn: 217037
* Document !and. Fix !shl and friends -- they provide binary operations.Joerg Sonnenberger2014-09-032-3/+3
| | | | llvm-svn: 217034
* Fix configure and make build of llvm examples.Iain Sandoe2014-09-039-9/+9
| | | | | | Replaced link component 'jit' with 'mcjit'. llvm-svn: 217032
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-0331-101/+73
| | | | | | No functionality change. Changes made by clang-tidy + some manual cleanup. llvm-svn: 217028
* Fix ambiguous call to make_unique and clang-format.Yaron Keren2014-09-031-13/+7
| | | | llvm-svn: 217023
* Follow-up for r217020: actually commit the fix for PR20800,Alexander Potapenko2014-09-032-14/+23
| | | | | | revert the accidentally committed changes to LLVMSymbolize.cpp llvm-svn: 217021
* Fix PR20800: correctly calculate the offset of the subq instruction when ↵Alexander Potapenko2014-09-032-1/+57
| | | | | | | | | | generating compact unwind info. This CL replaces the constant DarwinX86AsmBackend.PushInstrSize with a method that lets the backend account for different sizes of "push %reg" instruction sizes. llvm-svn: 217020
* Reapply r216805 "[MachineCombiner][AArch64] Use the correct register class ↵Juergen Ributzka2014-09-032-79/+148
| | | | | | | | | | | | | | | | for MADD, SUB, and OR."" This reapplies r216805 with a fix to a copy-past error, which resulted in an incorrect register class. Original commit message: Select the correct register class for the various instructions that are generated when combining instructions and constrain the registers to the appropriate register class. This fixes rdar://problem/18183707. llvm-svn: 217019
* Recommit "Use unique_ptr to manager FilterChooser ownership."Craig Topper2014-09-031-23/+16
| | | | | | Just using insert of a pair this time instead of emplace. llvm-svn: 217018
* Revert "Use unique_ptr to manager FilterChooser ownership."Craig Topper2014-09-031-15/+24
| | | | | | std::map::emplace isn't working on some of the bots. llvm-svn: 217015
* Use unique_ptr to manager FilterChooser ownership.Craig Topper2014-09-031-24/+15
| | | | llvm-svn: 217014
* Implement move constructor and remove copy constructor for Filter objects in ↵Craig Topper2014-09-031-13/+8
| | | | | | FixedLenDecoderEmitter. Also remove unused copy constructor of FilterChooser. llvm-svn: 217013
* [MCJIT] Make llvm-rtdyld process eh_frame sections in -verify mode (accidentallyLang Hames2014-09-032-1/+4
| | | | | | | | left out of r217010). Also remove a crufty debugging output statement that was accidentally left in. llvm-svn: 217011
* [MCJIT] Add a 'section_addr' builtin function to RuntimeDyldChecker.Lang Hames2014-09-033-25/+141
| | | | | | | | | | The syntax of the new builtin is 'section_addr(<filename>, <section-name>)' (similar to the stub_addr builtin, but without a symbol name). It returns the base address of the given section in the given object file. This builtin makes it possible to refer to the contents of sections that cannot contain symbols, e.g. sections added by the linker itself, like __eh_frame. llvm-svn: 217010
* [FastISel][AArch64] Add target-dependent instruction selection for Add/Sub.Juergen Ributzka2014-09-032-201/+178
| | | | | | | | | | | There is already target-dependent instruction selection support for Adds/Subs to support compares and the intrinsics with overflow check. This takes advantage of the existing infrastructure to also support Add/Sub, which allows the folding of immediates, sign-/zero-extends, and shifts. This fixes rdar://problem/18207316. llvm-svn: 217007
* Fix test case to match correct llvm-objdump outputNick Kledzik2014-09-031-3/+3
| | | | llvm-svn: 217006
* Replace printf with outs() <<Nick Kledzik2014-09-031-1/+1
| | | | llvm-svn: 217005
* Change name of copyFlags() to copyIRFlags(). Add convenience method for ↵Sanjay Patel2014-09-033-3/+24
| | | | | | | | | | logical 'and' of all flags. NFC. Adding 'IR' to the names in an attempt to be less ambiguous about the flags we're dealing with here. The 'and' method is needed by the SLPVectorizer (PR20802) and possibly other passes. llvm-svn: 217004
* [CFLAA] Remove one final initializer listHal Finkel2014-09-031-1/+5
| | | | | | Maybe MSVC will be happy now... llvm-svn: 217000
* [CFLAA] And even more MSVC fixesHal Finkel2014-09-022-3/+6
| | | | | | Remove a couple more initializer lists and constexpr dependencies. llvm-svn: 216998
* Cleaning up remaining static initializers in Signals.incChris Bieneman2014-09-021-24/+31
| | | | llvm-svn: 216996
* [CFLAA] More cleanup for MSVCHal Finkel2014-09-022-11/+14
| | | | | | Remove more initializer lists, etc. llvm-svn: 216994
* Tablegen scheduling models don't reference empty itineraries as of r216919, ↵Pete Cooper2014-09-021-4/+5
| | | | | | so don't emit the unused itinerary variables llvm-svn: 216993
* [CFLAA] No initializer lists for MSVCHal Finkel2014-09-022-28/+30
| | | | | | MSVC 2012 does not understand initializer lists; remove them. llvm-svn: 216991
* Missing test from r216989Renato Golin2014-09-021-0/+34
| | | | llvm-svn: 216990
* Only emit movw on ARMv6T2+Renato Golin2014-09-022-2/+3
| | | | | | | | Fix PR18364. Patch by Dimitry Andric. llvm-svn: 216989
* unique_ptrify passing the TargetMachine to ExecutionEngine::MCJITCtorDavid Blaikie2014-09-024-21/+16
| | | | llvm-svn: 216988
* [CFLAA] Remove tautological comparisonHal Finkel2014-09-021-1/+1
| | | | | | | | Fixes this (the warning is right, the unsigned value is not negative): lib/Analysis/StratifiedSets.h:689:53: warning: comparison of unsigned expression >= 0 is always true [-Wtautological-compare] bool inbounds(StratifiedIndex N) const { return N >= 0 && N < Links.size(); } llvm-svn: 216987
* [FastISel][AArch64] Use the target-dependent selection code for shifts first.Juergen Ributzka2014-09-023-29/+18
| | | | | | | | | | | | This uses the target-dependent selection code for shifts first, which allows us to create better code for shifts with immediates and sign-/zero-extend folding. Vector type are not handled yet and the code falls back to target-independent instruction selection for these cases. This fixes rdar://problem/17907920. llvm-svn: 216985
* [FastISel][AArch64] Use a new helper function to determine if a value type ↵Juergen Ributzka2014-09-021-6/+25
| | | | | | | | | | | | is supported. NFCI. FastISel for AArch64 supports more value types than are actually legal. Use a dedicated helper function to reflect this. It is very similar to the isLoadStoreTypeLegal function, with the exception that vector types are not supported yet. llvm-svn: 216984
* Nuke MCAnalysis.Sean Silva2014-09-0231-2854/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code is buggy and barely tested. It is also mostly boilerplate. (This includes MCObjectDisassembler, which is the interface to that functionality) Following an IRC discussion with Jim Grosbach, it seems sensible to just nuke the whole lot of functionality, and dig it up from VCS if necessary (I hope not!). All of this stuff appears to have been added in a huge patch dump (look at the timeframe surrounding e.g. r182628) where almost every patch seemed to be untested and not reviewed before being committed. Post-review responses to the patches were never addressed. I don't think any of it would have passed pre-commit review. I doubt anyone is depending on this, since this code appears to be extremely buggy. In limited testing that Michael Spencer and I did, we couldn't find a single real-world object file that wouldn't crash the CFG reconstruction stuff. The symbolizer stuff has O(n^2) behavior and so is not much use to anyone anyway. It seemed simpler to remove them as a whole. Most of this code is boilerplate, which is the only way it was able to scrape by 60% coverage. HEADSUP: Modules folks, some files I nuked were referenced from include/llvm/module.modulemap; I just deleted the references. Hopefully that is the right fix (one was a FIXME though!). llvm-svn: 216983
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-02258-12590/+184
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* [CFLAA] LLVM_CONSTEXPR -> constHal Finkel2014-09-021-1/+1
| | | | | | | The number is just a constant, and this should make MSVC happy (or at least happier). llvm-svn: 216981
* [X86] Allow atomic operations using immediates to avoid using a registerRobin Morisset2014-09-024-38/+669
| | | | | | | | | | | | | | | | The only valid lowering of atomic stores in the X86 backend was mov from register to memory. As a result, storing an immediate required a useless copy of the immediate in a register. Now these can be compiled as a simple mov. Similarily, adding/and-ing/or-ing/xor-ing an immediate to an atomic location (but through an atomic_store/atomic_load, not a fetch_whatever intrinsic) can now make use of an 'add $imm, x(%rip)' instead of using a register. And the same applies to inc/dec. This second point matches the first issue identified in http://llvm.org/bugs/show_bug.cgi?id=17281 llvm-svn: 216980
* [CFLAA] constexpr -> LLVM_CONSTEXPRHal Finkel2014-09-022-13/+15
| | | | | | Attempt to fix the MSVC build by not using constexpr. llvm-svn: 216979
* Add pass-manager flags to use CFL AAHal Finkel2014-09-022-0/+11
| | | | | | | Add -use-cfl-aa (and -use-cfl-aa-in-codegen) to add CFL AA in the default pass managers (for easy testing). llvm-svn: 216978
* BumpPtrAllocator: use uintptr_t when aligning addresses to avoid undefined ↵Hans Wennborg2014-09-023-23/+26
| | | | | | | | | behaviour In theory, alignPtr() could push a pointer beyond the end of the current slab, making comparisons with that pointer undefined behaviour. Use an integer type to avoid this. llvm-svn: 216973
* [asan] Assign a low branch weight to ASan's slow path, patch by Jonas ↵Kostya Serebryany2014-09-023-3/+8
| | | | | | Wagner. This speeds up asan (at least on SPEC) by 1%-5% or more. Also fix lint in dfsan. llvm-svn: 216972
* R600/SI: Relax some ordering in tests.Matt Arsenault2014-09-024-26/+31
| | | | | | This will help with enabling misched llvm-svn: 216971
* Add a CFL Alias Analysis implementationHal Finkel2014-09-0215-0/+1893
| | | | | | | | | | | | | | | | This provides an implementation of CFL alias analysis (including some supporting data structures). Currently, we don't have any extremely fancy features, sans some interprocedural analysis (i.e. no field sensitivity, etc.), and we do best sitting behind BasicAA + TBAA. In such a configuration, we take ~0.6-0.8% of total compile time, and give ~7-8% NoAlias responses to queries TBAA and BasicAA couldn't answer when bootstrapping LLVM. In testing this on other projects, we've seen up to 10.5% of queries dropped by BasicAA+TBAA answered with NoAlias by this algorithm. Patch by George Burgess IV (with minor modifications by me -- mostly adapting some BasicAA tests), thanks! llvm-svn: 216970
* [FastISel][AArch64] Move over to target-dependent instruction selection only.Juergen Ributzka2014-09-021-41/+133
| | | | | | | | | | | This change moves FastISel for AArch64 to target-dependent instruction selection only. This change replicates the existing target-independent behavior, therefore there are no changes to the unit tests or new tests. Future changes will take advantage of this change and update functionality and unit tests. llvm-svn: 216955
* [FastISel] Provide the option to skip target-independent instruction ↵Juergen Ributzka2014-09-022-21/+29
| | | | | | | | | | | | | selection. NFC. This allows the target to disable target-independent instruction selection and jump directly into the target-dependent instruction selection code. This can be beneficial for targets, such as AArch64, which could emit much better code, but never got a chance to do so, because the target-independent instruction selector was able to find an instruction sequence. llvm-svn: 216947
* Generate extract for in-tree uses if the use is scalar operand in vectorized ↵Yi Jiang2014-09-022-18/+139
| | | | | | instruction. radar://18144665 llvm-svn: 216946
* R600/SI: Fix hardcoded register numbers in testMatt Arsenault2014-09-021-1/+1
| | | | llvm-svn: 216944
* Refactor LowerFABS and LowerFNEG into one function (x86) (NFC)Sanjay Patel2014-09-021-42/+31
| | | | | | | | | We duplicate ~30 lines of code to lower FABS and FNEG for x86, so this patch combines them into one function. No functional change intended, so no additional test cases. Test-suite behavior is unchanged. Differential Revision: http://reviews.llvm.org/D5064 llvm-svn: 216942
* cmake: Don't reject unknown cpp files that start with .Matt Arsenault2014-09-021-4/+9
| | | | | | | | Some editors create hidden file backups in the same directory as the file, and it's annoying when cmake errors on them. llvm-svn: 216941
* Fix MemoryDependenceAnalysis in cases where QueryInstr is a CmpXchg or a ↵Robin Morisset2014-09-021-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AtomicRMW Summary: MemoryDependenceAnalysis is currently cautious when the QueryInstr is an atomic load or store, but I forgot to check for atomic cmpxchg/atomicrmw. This patch is a way of fixing that, and making it less brittle (i.e. no risk that I forget another possible kind of atomic, even if the IR ends up changing in the future), by adding a fallback checking mayReadOrWriteFromMemory. Thanks to Philip Reames for finding this bug and suggesting this solution in http://reviews.llvm.org/D4845 Sadly, I don't see how to add a test for this, since the passes depending on MemoryDependenceAnalysis won't trigger for an atomic rmw anyway. Does anyone see a way for testing it? Test Plan: none possible at first sight Reviewers: jfb, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5019 llvm-svn: 216940
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