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* [InstSimplify] reorder methods; NFCSanjay Patel2017-09-111-230/+229
| | | | | | | | | | | I'm trying to refactor some shared code for integer div/rem, but I keep having to scroll through fdiv. The FP ops have nothing in common with the integer ops, so I'm moving FP below everything else. While here, improve a couple of comments and fix some formatting. llvm-svn: 312913
* [X86][SSE] Add further test cases showing failure to compute sign bits ↵Simon Pilgrim2017-09-111-1/+388
| | | | | | | | | through PACKSS Suggested in D37680 Note: had to drop AVX512VL tests as there is an infinite loop in the new tests that needs further investigation (not relevant to D37680). llvm-svn: 312910
* [X86][SKX][KNL] Updating several CodeGen tests to use the attr flag instead ↵Gadi Haber2017-09-113-38/+40
| | | | | | | | | | | | | of mcpu flag NFC. Updated 3 Codegen regression tests to use the -mattr flag instead of the -mcpu flags as follows: Instead of -mcpu=skx use -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq Instead of -mcpu=knl use -mattr=+avx512f Reviewers: delena Revision: https://reviews.llvm.org/D37674 llvm-svn: 312909
* [ARM] Enable the use of SVC anywhere in an IT blockAndre Vieira2017-09-112-3/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D37374 llvm-svn: 312908
* [Interleved][Stride 3]Adding test for case the VF=64 target with AVX512.Michael Zuckerman2017-09-113-0/+661
| | | | llvm-svn: 312907
* [X86][SSE] Add test showing failure to compute sign bits through PACKSSSimon Pilgrim2017-09-111-0/+65
| | | | | | Prevents combineLogicBlendIntoPBLENDV from merging to PBLENDV llvm-svn: 312906
* [AVR] Enable the '__do_copy_data' functionDylan McKay2017-09-114-0/+32
| | | | | | | | | | | | | Also enables '__do_clear_bss'. These functions are automaticalled called by the CRT if they are declared. We need these to be called otherwise RAM will start completely uninitialised, even though we need to copy RAM variables from progmem to RAM. llvm-svn: 312905
* [GlobalISel][X86] G_ANYEXT support.Igor Breger2017-09-116-7/+666
| | | | | | | | | | | | | | Summary: G_ANYEXT support Reviewers: zvi, delena Reviewed By: delena Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D37675 llvm-svn: 312903
* Fixed a typo in llvm-cov/deferred-region.cpp test.Ilya Biryukov2017-09-111-1/+1
| | | | | | Input redirection was using `2&>1` instead of `2>&1`. llvm-svn: 312902
* AMDGPU: trivial comment changeTim Renouf2017-09-111-1/+1
| | | | | | ... to check commit access for new committer. llvm-svn: 312900
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-09-114-35/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515 and also is being recommitted as its first version caused PR34045. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 312898
* Fixed a bug in splitting Scatter operation in the Type Legalizer.Elena Demikhovsky2017-09-112-11/+9
| | | | | | | | | After the split of the Scatter operation, the order of the new instructions is well defined - Lo goes before Hi. Otherwise the semantic of Scatter (from LSB to MSB) is broken. I'm chaining 2 nodes to prevent reordering. Differential Revision https://reviews.llvm.org/D37670 llvm-svn: 312894
* [ORC] Kill off a dead typedef.Lang Hames2017-09-111-6/+0
| | | | llvm-svn: 312893
* Use llvm_unreachable for unknown TargetCostKind.Simon Pilgrim2017-09-101-2/+1
| | | | | | TargetTransformInfo::getInstructionCost's switch covers all TargetCostKind cases so we shouldn't return for a default case. llvm-svn: 312888
* [X86][SSE] Tidyup + clang-format combineX86ShuffleChain call. NFCI.Simon Pilgrim2017-09-101-3/+2
| | | | llvm-svn: 312887
* [X86][SSE] Move combineTo call out of combineX86ShufflesConstants. NFCI.Simon Pilgrim2017-09-101-11/+13
| | | | | | Move towards making it possible to use the shuffle combines for cases where we don't want to call DCI.CombineTo() with the result. llvm-svn: 312886
* [InstSimplify] refactor udiv/urem code and add tests; NFCISanjay Patel2017-09-103-18/+168
| | | | | | | | | This removes some duplicated code and makes it easier to support signed div/rem in a similar way if we want to do that. Note that the existing comments were not accurate - we don't need a constant divisor to simplify; icmp simplification does more than that. But as the added tests show, it could go even further. llvm-svn: 312885
* [X86][SSE] Move combineTo call out of combineX86ShuffleChain. NFCI.Simon Pilgrim2017-09-101-74/+46
| | | | | | First step towards making it possible to use the shuffle combines for cases where we don't want to call DCI.CombineTo() with the result. llvm-svn: 312884
* Added a test that demonstrates a ug in Scatter scheduling.Elena Demikhovsky2017-09-101-0/+23
| | | | | | | The bug is going to be fixed in an upcomming patch. llvm-svn: 312883
* [X86][X86AsmParser] adding const on InlineAsmIdentifierInfo in ↵Coby Tayree2017-09-101-2/+2
| | | | | | CreateMemForInlineAsm. NFC. llvm-svn: 312881
* Revert "adding autoUpgrade support to broadcast[f|i]32x2 intrinsics"Uriel Korach2017-09-103-20/+31
| | | | | | This reverts commit r312879 - An accidental partial commit. llvm-svn: 312880
* adding autoUpgrade support to broadcast[f|i]32x2 intrinsicsUriel Korach2017-09-103-31/+20
| | | | llvm-svn: 312879
* Test commitUriel Korach2017-09-101-1/+1
| | | | llvm-svn: 312878
* [SCEV] Re-arrange public and private sections to be contiguous; NFCSanjoy Das2017-09-101-539/+536
| | | | llvm-svn: 312876
* [X86] Add v2i4 store test case (PR20012)Simon Pilgrim2017-09-091-0/+17
| | | | llvm-svn: 312874
* [X86] Add v2i2 test case (PR20011)Simon Pilgrim2017-09-091-0/+33
| | | | llvm-svn: 312873
* [X86][FMA] Regenerate FMA testsSimon Pilgrim2017-09-094-715/+910
| | | | llvm-svn: 312871
* Merge isKnownNonNull into isKnownNonZeroNuno Lopes2017-09-0917-149/+142
| | | | | | | | | It now knows the tricks of both functions. Also, fix a bug that considered allocas of non-zero address space to be always non null Differential Revision: https://reviews.llvm.org/D37628 llvm-svn: 312869
* [X86][SSE] i32 vector multiplications test cases from PR6399Simon Pilgrim2017-09-091-0/+472
| | | | llvm-svn: 312868
* [X86][MOVBE] Fix typo in MOVBE scheduling test namesSimon Pilgrim2017-09-091-21/+21
| | | | | | Copy+paste is not your friend llvm-svn: 312867
* [X86] Don't disable slow INC/DEC if optimizing for sizeCraig Topper2017-09-095-33/+28
| | | | | | | | | | | | | | | | | Summary: Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size. This appears to match gcc behavior. Reviewers: chandlerc, zvi, RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37177 llvm-svn: 312866
* [CMake] Update GetSVN.cmake to handle repoMinSeong Kim2017-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When repo is used with git, 'clang --version' option does not display the correct revision information (i.e. git hash on TOP) as the following: clang version 6.0.0 ---> clang version 6.0.0 (clang version) (llvm version) This is because repo also creates .git/svn folder as git-svn does and this makes repo with git uses "git svn info" command, which is only for git-svn, to retrieve its revision information, making null for the info. To correctly distinguish between git-svn and repo with git, the folder hierarchy to specify for git-svn should be .git/svn/refs as the "git svn info" command depends on the revision data in .git/svn/refs. This patch in turn makes repo with git passes through to the third macro, get_source_info_git, in get_source_info function, resulting in correctly retrieving the revision information for repo with git using "git log ..." command. This patch is tested with git, svn, git-svn, and repo with git. Reviewers: llvm-commits, probinson, rnk Reviewed By: rnk Subscribers: rnk, mehdi_amini, beanz, mgorny Differential Revision: https://reviews.llvm.org/D35532 llvm-svn: 312864
* [DivRemPairs] split tests per target to account for bots that don't build ↵Sanjay Patel2017-09-095-364/+606
| | | | | | for all targets llvm-svn: 312863
* [DivRempairs] add a pass to optimize div/rem pairs (PR31028)Sanjay Patel2017-09-0917-0/+647
| | | | | | | | | | | | | | | | | | This is intended to be a superset of the functionality from D31037 (EarlyCSE) but implemented as an independent pass, so there's no stretching of scope and feature creep for an existing pass. I also proposed a weaker version of this for SimplifyCFG in D30910. And I initially had almost this same functionality as an addition to CGP in the motivating example of PR31028: https://bugs.llvm.org/show_bug.cgi?id=31028 The advantage of positioning this ahead of SimplifyCFG in the pass pipeline is that it can allow more flattening. But it needs to be after passes (InstCombine) that could sink a div/rem and undo the hoisting that is done here. Decomposing remainder may allow removing some code from the backend (PPC and possibly others). Differential Revision: https://reviews.llvm.org/D37121 llvm-svn: 312862
* CoverageMappingTest.cpp: Suppress warnings. [-Wdocumentation]NAKAMURA Takumi2017-09-091-6/+6
| | | | llvm-svn: 312861
* [X86] Call removeDeadNode when we're done doing custom isel for mul, div and ↵Craig Topper2017-09-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | test Summary: Once we've done our custom isel for these nodes, I think we should be calling removeDeadNode to prune them out of the DAG. Table driven isel ultimately either calls morphNodeTo which modifies a node and doesn't leave dead nodes. Or it emits new nodes and then calls removeDeadNode as part of Opc_CompleteMatch. If you run a simple multiply test case like this through llc with -debug you'll see a umul_lohi node get printed as part of the dump for Instruction Selection ends. ``` define i64 @foo(i64 %a, i64 %b) local_unnamed_addr #0 { entry: %conv = zext i64 %a to i128 %conv1 = zext i64 %b to i128 %mul = mul nuw nsw i128 %conv1, %conv %shr = lshr i128 %mul, 64 %conv2 = trunc i128 %shr to i64 ret i64 %conv2 } ``` Reviewers: RKSimon, spatel, zvi, guyblank, niravd Reviewed By: niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37547 llvm-svn: 312857
* [X86] Use ReplaceNode instead of ReplaceUses when converting ↵Craig Topper2017-09-091-1/+1
| | | | | | | | X86ISD::SHRUNKBLEND to ISD::VSELECT during isel. This ensures that the SHRUNKBLEND node gets erased immediately. llvm-svn: 312856
* [sanitizer-coverage] call appendToUsed once per module, not once per ↵Kostya Serebryany2017-09-091-8/+8
| | | | | | function (which is too slow) llvm-svn: 312855
* [SLP] Fix buildbots, NFC.Alexey Bataev2017-09-091-2/+2
| | | | llvm-svn: 312853
* RegAllocFast: Fix warning; NFCMatthias Braun2017-09-091-2/+1
| | | | llvm-svn: 312852
* RegAllocFast: Cleanup; NFCMatthias Braun2017-09-093-301/+298
| | | | | | | | | | | | | - Use range based for - Variable names should start with upper case - Add `const` - Change class name to match filename - Fix doxygen comments - Use MCPhysReg instead of unsigned - Use references instead of pointers where things cannot be nullptr - Misc coding style improvements llvm-svn: 312846
* RegAllocFast: Move vector to class level to avoid reallocation; NFCMatthias Braun2017-09-091-2/+5
| | | | llvm-svn: 312845
* RegAllocFast: Remove write-only set; NFCMatthias Braun2017-09-091-10/+0
| | | | llvm-svn: 312844
* PPC: Don't select lxv/stxv for insufficiently aligned stack slots.Kyle Butt2017-09-092-1/+57
| | | | | | | | | | | | | | The lxv/stxv instructions require an offset that is 0 % 16. Previously we were selecting lxv/stxv for loads and stores to the stack where the offset from the slot was a multiple of 16, but the stack slot was not 16 or more byte aligned. When the frame gets lowered these transform to r(1|31) + slot + offset. If slot is not aligned, slot + offset may not be 0 % 16. Now we require 16 byte or more alignment for select lxv/stxv to stack slots. Includes a testcase that shows both sufficiently and insufficiently aligned stack slots. llvm-svn: 312843
* bpf: fix test failures due to previous bpf change of assembly code syntaxYonghong Song2017-09-095-6/+6
| | | | | Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 312840
* [AMDGPU] Remove unused function. NFCI.Davide Italiano2017-09-081-9/+0
| | | | llvm-svn: 312836
* [TargetTransformInfo] Remove the extra "default" in a switch that all enum ↵Guozhi Wei2017-09-081-4/+2
| | | | | | | | values has been covered. In function TargetTransformInfo::getInstructionCost, all enum values in the switch statement has been covered, so the default is unnecessary, and may cause error with option -Werror,-Wcovered-switch-default, so remove it. llvm-svn: 312834
* bpf: proper print imm64 expression in inst printerYonghong Song2017-09-082-2/+4
| | | | | | | | | | | | | | Fixed an issue in printImm64Operand where if the value is an expression, print out the expression properly. Currently, it will print r1 = <MCOperand Expr:(tx_port)>ll With the patch, the printout will be r1 = tx_port Suggested-by: Jiong Wang <jiong.wang@netronome.com> Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 312833
* [TargetTransformInfo] Add a new public interface getInstructionCostGuozhi Wei2017-09-086-562/+662
| | | | | | | | | | | | | | | | | | | | | | | | | | Current TargetTransformInfo can support throughput cost model and code size model, but sometimes we also need instruction latency cost model in different optimizations. Hal suggested we need a single public interface to query the different cost of an instruction. So I proposed following interface: enum TargetCostKind { TCK_RecipThroughput, ///< Reciprocal throughput. TCK_Latency, ///< The latency of instruction. TCK_CodeSize ///< Instruction code size. }; int getInstructionCost(const Instruction *I, enum TargetCostKind kind) const; All clients should mainly use this function to query the cost of an instruction, parameter <kind> specifies the desired cost model. This patch also provides a simple default implementation of getInstructionLatency. The default getInstructionLatency provides latency numbers for only small number of instruction classes, those latency numbers are only reasonable for modern OOO processors. It can be extended in following ways: Add more detail into this function. Add getXXXLatency function and call it from here. Implement target specific getInstructionLatency function. Differential Revision: https://reviews.llvm.org/D37170 llvm-svn: 312832
* [CMake][runtimes] Use the same configuration for non-target and "default" targetPetr Hosek2017-09-081-97/+106
| | | | | | | | | | | | | | The default host target for builtins and runtimes has special behavior on some platforms, e.g. on Linux both i386 and x86_64 targets are being built. Specifying "default" as a target name should lead to the same behavior, which wasn't the case in the past. This patch unifies the configuration between the non-target and "default" target to produce the same behavior by moving the default configuration into a function that can be used from both paths. Differential Revision: https://reviews.llvm.org/D37450 llvm-svn: 312831
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