| Commit message (Collapse) | Author | Age | Files | Lines |
| ... | |
| |
|
|
|
|
|
| |
constraint. Reject asms where an output has multiple
input constraints tied to it.
llvm-svn: 57687
|
| |
|
|
|
|
|
| |
array. Improve some minor comments, refactor some helpers in
AsmOperandInfo. No functionality change for valid code.
llvm-svn: 57686
|
| |
|
|
| |
llvm-svn: 57677
|
| |
|
|
|
|
|
|
|
|
| |
distinguished from normal (untagged) ones
as per review comment.
I am sufficiently unaquainted with doxygen to
defer the markup to someone with more experience.
llvm-svn: 57676
|
| |
|
|
|
|
| |
of aliases.
llvm-svn: 57673
|
| |
|
|
|
|
|
| |
should work for intel long double, but ppc long double aborts
in convert.
llvm-svn: 57672
|
| |
|
|
|
|
|
|
| |
constants that don't fit in an int. This fixes
"this decimal constant is unsigned only in ISO C90"
warnings.
llvm-svn: 57668
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.
A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.
To support this, teach tablegen how to handle 64-bit constants.
llvm-svn: 57663
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.
Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.
Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.
These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.
llvm-svn: 57662
|
| |
|
|
| |
llvm-svn: 57660
|
| |
|
|
| |
llvm-svn: 57653
|
| |
|
|
| |
llvm-svn: 57649
|
| |
|
|
| |
llvm-svn: 57644
|
| |
|
|
|
|
|
|
|
|
|
|
| |
using the 'volatile' qualifier. This should not have any operational consequences
on code, because tags should always be stripped off (giving a non-volatile pointer)
before dereferencing. The new qualification is there to catch some attempts to use
tagged pointers in a context where an untagged pointer is appropriate.
Notably this approach does not catch dereferencing of tagged pointers, but helps
in separating the two concepts a bit.
llvm-svn: 57641
|
| |
|
|
| |
llvm-svn: 57636
|
| |
|
|
|
|
| |
uninitialized in these functions with gcc-4.3.
llvm-svn: 57635
|
| |
|
|
|
|
| |
warning on x86-64 with gcc-4.3.
llvm-svn: 57634
|
| |
|
|
| |
llvm-svn: 57633
|
| |
|
|
| |
llvm-svn: 57631
|
| |
|
|
|
|
|
| |
x86 backend. These will all be answered with "patches welcome", so
a PR doesn't help drive them along.
llvm-svn: 57630
|
| |
|
|
|
|
|
| |
basically working, feel free to remove the tag. The other targets have
really basic things that break them.
llvm-svn: 57628
|
| |
|
|
| |
llvm-svn: 57626
|
| |
|
|
| |
llvm-svn: 57625
|
| |
|
|
| |
llvm-svn: 57622
|
| |
|
|
| |
llvm-svn: 57621
|
| |
|
|
|
|
|
| |
additional information in Loads, Stores, Calls, Invokes,
InsertValueInsts, and ExtractValueInsts.
llvm-svn: 57620
|
| |
|
|
| |
llvm-svn: 57619
|
| |
|
|
| |
llvm-svn: 57618
|
| |
|
|
|
|
|
|
| |
because it declares a std::vector<MachineMove>, and strict
concept checking requires the definition of MachineMove to be
available.
llvm-svn: 57617
|
| |
|
|
|
|
|
| |
copies of a value, and add several additional utilities to make
SmallVector better conform to the Container concept.
llvm-svn: 57616
|
| |
|
|
|
|
| |
passing in a function object.
llvm-svn: 57615
|
| |
|
|
|
|
|
| |
computation. A def of a register doesn't necessarily kill
live super-registers.
llvm-svn: 57614
|
| |
|
|
|
|
| |
an unindexed load.
llvm-svn: 57612
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
to find opportunities for store-to-load forwarding or load CSE,
in the same way that visitStore scans back to do DSE. Also, define
a new helper function for testing whether the addresses of two
memory accesses are known to have the same value, and use it in
both visitStore and visitLoad.
These two changes allow instcombine to eliminate loads in code
produced by front-ends that frequently emit obviously redundant
addressing for memory references.
llvm-svn: 57608
|
| |
|
|
| |
llvm-svn: 57606
|
| |
|
|
| |
llvm-svn: 57605
|
| |
|
|
| |
llvm-svn: 57604
|
| |
|
|
| |
llvm-svn: 57599
|
| |
|
|
| |
llvm-svn: 57597
|
| |
|
|
| |
llvm-svn: 57596
|
| |
|
|
| |
llvm-svn: 57595
|
| |
|
|
| |
llvm-svn: 57594
|
| |
|
|
| |
llvm-svn: 57590
|
| |
|
|
|
|
| |
This fixes PR2894.
llvm-svn: 57589
|
| |
|
|
| |
llvm-svn: 57587
|
| |
|
|
| |
llvm-svn: 57586
|
| |
|
|
|
|
| |
with the build directory different from the source directory.
llvm-svn: 57583
|
| |
|
|
| |
llvm-svn: 57582
|
| |
|
|
| |
llvm-svn: 57579
|
| |
|
|
| |
llvm-svn: 57578
|