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* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-162-2/+31
| | | | | | | | | | In Thumb mode we cannot handle GPR virtual registers, even though some instructions can. When isel is lowering a CopyFromReg, it should limit itself to subclasses of getRegClassFor(VT). <rdar://problem/9624323> llvm-svn: 133210
* Regenerate configure.Daniel Dunbar2011-06-161-3/+21
| | | | llvm-svn: 133207
* build/configure: Add support for --with-extra-ld-options flag (to provide extraDaniel Dunbar2011-06-163-0/+18
| | | | | | options just to pass to ld). llvm-svn: 133206
* Added LLVM_BUILD_MODE to cmake so that lit supports tests with REQUIRES: ↵Andrew Trick2011-06-162-1/+6
| | | | | | {buildmode}. llvm-svn: 133205
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-165-33/+39
| | | | | | No functional change was intended. llvm-svn: 133202
* forward declare GraphTraits in Type.h instead of #includ'ing it.Chris Lattner2011-06-161-1/+1
| | | | llvm-svn: 133201
* cmake may require LIT_TOOLS_DIR.Andrew Trick2011-06-161-0/+1
| | | | | | Reviewed by chapuni. Sorry for breaking. llvm-svn: 133200
* change Type.h to forward declare ArrayRef instead of #including it.Chris Lattner2011-06-162-10/+14
| | | | llvm-svn: 133197
* add some #includes that will soon be needed.Chris Lattner2011-06-162-0/+2
| | | | llvm-svn: 133195
* prune #includes.Chris Lattner2011-06-161-19/+5
| | | | llvm-svn: 133194
* move the address space into the subclass data field, saving a word on ↵Chris Lattner2011-06-162-5/+4
| | | | | | | | PointerType. This limits the # address spaces to 2^23, which should be good enough. llvm-svn: 133192
* tidy up some comments, store the 'isvararg' bit for FunctionType inChris Lattner2011-06-162-45/+35
| | | | | | the SubclassData field, saving a word. llvm-svn: 133191
* remove Type::getVAArgsPromotedType, which is dead, and tidy up a bit.Chris Lattner2011-06-163-20/+8
| | | | llvm-svn: 133190
* There's no need to be so picky about the particular register.Nick Lewycky2011-06-161-4/+4
| | | | llvm-svn: 133189
* Fix ARCOpt to insert releases on both successors of an invoke ratherDan Gohman2011-06-162-10/+94
| | | | | | than trying to insert them immediately after the invoke. llvm-svn: 133188
* Move PBQP off allocation_order_begin. No functional change intended.Jakob Stoklund Olesen2011-06-161-5/+4
| | | | | | | I think PBQP could use RegisterClassInfo, but it didn't fit neatly with the external interfaces that PBQP uses, so I'll leave that to Lang. llvm-svn: 133186
* Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak2011-06-1612-27/+356
| | | | | | | | BranchProbabilityInfo (expect setEdgeWeight which is not available here). Branch Weights are kept in MachineBasicBlocks. To turn off this analysis set -use-mbpi=false. llvm-svn: 133184
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its ↵Owen Anderson2011-06-163-17/+33
| | | | | | | | first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change. This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON. llvm-svn: 133178
* Switch linear scan to using RegisterClassInfo.Jakob Stoklund Olesen2011-06-161-18/+12
| | | | | | | | | This avoids the manual filtering of reserved registers and removes the dependency on allocation_order_begin(). Palliative care... llvm-svn: 133177
* Move test for appropriate directory.Galina Kistanova2011-06-161-0/+0
| | | | llvm-svn: 133176
* Mark ldrexd/strexd w/ volatile memory by defaultBruno Cardoso Lopes2011-06-161-2/+2
| | | | llvm-svn: 133175
* Test commit.Jakub Staszak2011-06-161-7/+7
| | | | llvm-svn: 133174
* PTX: Finish new calling convention implementationJustin Holewinski2011-06-1622-205/+315
| | | | llvm-svn: 133172
* PTX: Rename register classes for readability and combine int and fp registersJustin Holewinski2011-06-167-741/+378
| | | | llvm-svn: 133171
* Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen2011-06-164-18/+43
| | | | | | | | | | | | | This virtual function will replace allocation_order_begin/end as the one to override when implementing custom allocation orders. It is simpler to have one function return an ArrayRef than having two virtual functions computing different ends of the same array. Use getRawAllocationOrder() in place of allocation_order_begin() where it makes sense, but leave some clients that look like they really want the filtered allocation orders from RegisterClassInfo. llvm-svn: 133170
* Add testcase for r133050 which added support for printing and parsing escapedNick Lewycky2011-06-161-0/+24
| | | | | | names for named metadata nodes. llvm-svn: 133166
* Fix formatting.Owen Anderson2011-06-163-5/+5
| | | | llvm-svn: 133164
* Document nonlazybind.Dan Gohman2011-06-161-0/+5
| | | | llvm-svn: 133160
* Add a comment describing why transforming (shl x, 1) to (add x, x) is to beDan Gohman2011-06-161-0/+5
| | | | | | considered safe enough in this context. llvm-svn: 133159
* PTX: Fix whitespace errorsJustin Holewinski2011-06-164-25/+27
| | | | llvm-svn: 133158
* Add AVX suport for fpextend.Bruno Cardoso Lopes2011-06-162-0/+29
| | | | | | Original patch by Syoyo Fujita with more comments by me. llvm-svn: 133153
* Prempt some obnoxious compiler from complaing about signed/unsignedJakob Stoklund Olesen2011-06-161-2/+2
| | | | | | | | | compares. 2^30 is actually the limit on the number of physical registers per TargetRegisterInfo.h. llvm-svn: 133142
* Make sure to pass an unsigned to a printf format that is always %u.Jakob Stoklund Olesen2011-06-161-1/+6
| | | | | | This should unbreak the native ARM testers. llvm-svn: 133141
* FileCheck-ize test, and make it work on EABI hosts, like ↵Eli Friedman2011-06-161-7/+34
| | | | | | clang-native-arm-cortex-a9. llvm-svn: 133139
* Force a triple here so this test doesn't fail on EABI hosts (like ↵Eli Friedman2011-06-161-1/+1
| | | | | | clang-native-arm-cortex-a9). llvm-svn: 133134
* Commit the right set of tests for r133124. Sorry 'bout that!Nick Lewycky2011-06-162-4/+9
| | | | llvm-svn: 133133
* Reenabling this test with REQUIRES: AssertsAndrew Trick2011-06-161-3/+2
| | | | llvm-svn: 133132
* Add support to lit for build mode requirements. e.g.Andrew Trick2011-06-164-3/+13
| | | | | | | | | | REQUIRES: Asserts REQUIRES: Debug This required chaining test configuration properties. It seems like a generally good thing to do. llvm-svn: 133131
* Typos.Chad Rosier2011-06-161-4/+4
| | | | llvm-svn: 133128
* Revision r128665 added an optimization to make use of NEON multiplierChad Rosier2011-06-162-1/+23
| | | | | | | | | | | | | | | | | accumulator forwarding. Specifically (from SVN log entry): Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was intended in the original revision. llvm-svn: 133127
* Add a DAGCombine for (ext (binop (load x), cst)).Nick Lewycky2011-06-163-63/+157
| | | | llvm-svn: 133124
* Silence warnings in non assert builds. Patch by David BlaikieBruno Cardoso Lopes2011-06-161-2/+2
| | | | llvm-svn: 133118
* Rename the test. Thanks Cameron! Use shorter/generic names.Anna Zaks2011-06-161-12/+12
| | | | llvm-svn: 133115
* Function::getNumBlockIDs() should be used instead of Function::size() to set ↵Anna Zaks2011-06-162-1/+82
| | | | | | the upper limit on the block IDs since basic blocks might get removed (simplified away) after being initially numbered. Plus the test case, in which SelectionDAGBuilder::visitBr() calls llvm::MachineFunction::removeFromMBBNumbering(), which introduces the hole in numbering leading to an assert in llc (prior to the fix). llvm-svn: 133113
* Add a limit to the number of instructions memdep will scan in a single ↵Eli Friedman2011-06-151-1/+22
| | | | | | | | | | block. This prevents (at least in some cases) O(N^2) runtime in passes like DSE. The limit in this patch is probably too high, but it is enough to stop DSE from going completely insane on a testcase I have (which has a single block with around 50,000 non-aliasing stores in it). rdar://9471075 llvm-svn: 133111
* The ARC language-specific optimizer. Credit to Dan Gohman.John McCall2011-06-1528-0/+6947
| | | | llvm-svn: 133108
* unittests: add test for APInt::toString()Dylan Noblesmith2011-06-151-0/+46
| | | | | | Follow up to r133032. llvm-svn: 133107
* Add a new MVT::untyped. This will be used in future work for modelling ISA ↵Owen Anderson2011-06-155-10/+54
| | | | | | features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. llvm-svn: 133106
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-1515-547/+255
| | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. llvm-svn: 133105
* Update the Clang diagnostic emitter to emit IDs for diagnostic categories.John McCall2011-06-151-1/+11
| | | | | | Patch by Argyrios Kyrtzidis. llvm-svn: 133093
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