summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* Avoid doing a lot of computation when we have multiple ranges andEric Christopher2013-07-031-26/+29
| | | | | | | avoid adding information for the debug_inlined section when it isn't going to be emitted anyhow. llvm-svn: 185500
* SystemZInstrInfo.cpp: Tweak an assertion. [-Wunused-variable]NAKAMURA Takumi2013-07-031-2/+2
| | | | llvm-svn: 185499
* Move iterator to where it's used and update comments.Eric Christopher2013-07-031-1/+3
| | | | llvm-svn: 185498
* Move instance variable before experimental section.Eric Christopher2013-07-031-4/+5
| | | | llvm-svn: 185497
* Fix typo to make grep for DW_AT_comp_dir work without case-insensitiveEric Christopher2013-07-031-1/+1
| | | | | | grep. llvm-svn: 185496
* Remove unnecessary forward declare.Eric Christopher2013-07-031-1/+0
| | | | llvm-svn: 185495
* Add a helpful comment.Eric Christopher2013-07-031-0/+2
| | | | llvm-svn: 185492
* addConstantValue, addConstantFPValue never returned anything butEric Christopher2013-07-032-30/+18
| | | | | | true, so remove the return value and propagate accordingly. llvm-svn: 185490
* Trying to fix the botsManman Ren2013-07-031-2/+6
| | | | llvm-svn: 185489
* Debug Info: use module flag to set up Dwarf version.Manman Ren2013-07-026-6/+73
| | | | | | | | Correctly handles ref_addr depending on the Dwarf version. Emit Dwarf with version from module flag. TODO: turn on/off features depending on the Dwarf version. llvm-svn: 185484
* Fix comment.Eric Christopher2013-07-021-1/+1
| | | | llvm-svn: 185480
* Fixed typo in LangRef where we were using _'' to quote instead of the correct _.Michael Gottesman2013-07-021-1/+1
| | | | llvm-svn: 185479
* [PowerPC] PR16512 - Support TLS call sequences in the asm parserUlrich Weigand2013-07-023-2/+40
| | | | | | | | | This patch now adds support for recognizing TLS call sequences in the asm parser. This needs a new pattern BL8_TLS, which is like BL8_NOP_TLS except without nop. That pattern is used for the asm parser only. llvm-svn: 185478
* [PowerPC] Rework TLS call operand processingUlrich Weigand2013-07-026-23/+40
| | | | | | | | | | | | | | | | | | | | | | | | | As part of the global-dynamic and local-dynamic TLS sequences, we need to use a special form of the call instruction: bl __tls_get_addr(sym@tlsld) bl __tls_get_addr(sym@tlsgd) which generates two fixups. The current implementation of this causes problems with recognizing this form in the asm parser. To fix this, this patch reworks operand processing for this special form by using a single operand to hold both __tls_get_addr and sym@tlsld and defining a print method to output the above form, and an encoding method to generate the two fixups. As a side simplification, the patch replaces the two instruction patterns BL8_NOP_TLSGD and BL8_NOP_TLSLD by a single BL8_NOP_TLS, since the patterns already operate in an identical fashion (whether we have a local-dynamic or global-dynamic symbol is already encoded in the symbol modifier). No change in code generation intended. llvm-svn: 185477
* [PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLDUlrich Weigand2013-07-028-15/+7
| | | | | | | | | | | | | | | The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD. This causes some confusion with the asm parser, since VK_PPC_TLSGD is output as @tlsgd, which is then read back in as VK_TLSGD. To avoid this confusion, this patch removes the PowerPC-specific modifiers and uses the generic modifiers throughout. (The only drawback is that the generic modifiers are printed in upper case while the usual convention on PowerPC is to use lower-case modifiers. But this is just a cosmetic issue.) llvm-svn: 185476
* SystemZ: Fold variable into assertion.Benjamin Kramer2013-07-021-2/+2
| | | | llvm-svn: 185475
* Add 'REQUIRES: object-emission' to DebugInfo/inlined-arguments.ll.Jyotsna Verma2013-07-021-0/+2
| | | | llvm-svn: 185465
* [PowerPC] Support TLS variables in debug infoUlrich Weigand2013-07-024-3/+53
| | | | | | | | | This adds an implementation of getDebugThreadLocalSymbol for (64-bit) PowerPC. This needs to return a generic MCExpr since on ppc64, we need to add a bias of 0x8000 to the value returned by the R_PPC64_DTPREL64 relocation. llvm-svn: 185461
* [DebugInfo] Allow getDebugThreadLocalSymbol to return MCExprUlrich Weigand2013-07-025-7/+7
| | | | | | | | | | | This allows getDebugThreadLocalSymbol to return a generic MCExpr instead of just a MCSymbolRefExpr. This is in preparation for supporting debug info for TLS variables on PowerPC, where we need to describe the variable location using a more complex expression than just MCSymbolRefExpr. llvm-svn: 185460
* [DebugInfo] Hold generic MCExpr in AddrPoolUlrich Weigand2013-07-022-9/+9
| | | | | | | | | | | This changes the AddrPool infrastructure to enable it to hold generic MCExpr expressions, not just MCSymbolRefExpr. This is in preparation for supporting debug info for TLS variables on PowerPC, where we need to describe the variable location using a more complex expression than just MCSymbolRefExpr. llvm-svn: 185459
* [DebugInfo] Introduce DIEExpr variant of DIEValue to hold MCExpr valuesUlrich Weigand2013-07-025-21/+80
| | | | | | | | | | | | This partially reverts r185202 and restores DIELabel to hold plain MCSymbol references. Instead, we add a new subclass DIEExpr of DIEValue that can hold generic MCExpr references. This is in preparation for supporting debug info for TLS variables on PowerPC, where we need to describe the variable location using a more complex expression than just MCSymbolRefExpr. llvm-svn: 185458
* Debug Info: cleanupManman Ren2013-07-022-6/+8
| | | | llvm-svn: 185456
* Revert (most of) r185393 and r185395.Jakob Stoklund Olesen2013-07-022-80/+82
| | | | | | | | | | | "Remove floating point computations form SpillPlacement.cpp." These commits caused test failures in lencod on clang-native-arm-lnt. I suspect these changes are only exposing an existing issue, but reverting anyway to keep the bots passing while we investigate. llvm-svn: 185447
* Hexagon: Avoid unused variable warnings in Release builds.Benjamin Kramer2013-07-021-6/+2
| | | | llvm-svn: 185445
* Fix -Wsign-compare warning and remove windows-style line endings introduced ↵David Blaikie2013-07-021-17/+17
| | | | | | by r185421 llvm-svn: 185443
* [APFloat] Swap an early out check so we do not dereference str.end().Michael Gottesman2013-07-021-1/+1
| | | | | | | Originally if D.firstSigDigit == str.end(), we will have already dereferenced D.firstSigDigit in the first predicate. llvm-svn: 185437
* Remove address spaces from MC.Rafael Espindola2013-07-0224-209/+153
| | | | | | | | This is dead code since PIC16 was removed in 2010. The result was an odd mix, where some parts would carefully pass it along and others would assert it was zero (most of the object streamer for example). llvm-svn: 185436
* [SystemZ] Use DSGFR over DSGR in more casesRichard Sandiford2013-07-026-6/+49
| | | | | | | | | | Fixes some cases where we were using full 64-bit division for (sdiv i32, i32) and (sdiv i64, i32). The "32" in "SDIVREM32" just refers to the second operand. The first operand of all *DIVREM*s is a GR128. llvm-svn: 185435
* [SystemZ] Use MVC to spill loads and storesRichard Sandiford2013-07-026-13/+582
| | | | | | | | | | | | | | | | | | | | | Try to use MVC when spilling the destination of a simple load or the source of a simple store. As explained in the comment, this doesn't yet handle the case where the load or store location is also a frame index, since that could lead to two simultaneous scavenger spills, something the backend can't handle yet. spill-02.py tests that this restriction kicks in, but unfortunately I've not yet found a case that would fail without it. The volatile trick I used for other scavenger tests doesn't work here because we can't use MVC for volatile accesses anyway. I'm planning on relaxing the restriction later, hopefully with a test that does trigger the problem... Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly classified as SimpleBDX{Load,Store}. It wouldn't be easy to test for that bug separately, which is why I didn't split out the fix as a separate patch. llvm-svn: 185434
* [SystemZ] Add the MVC instructionRichard Sandiford2013-07-0211-127/+325
| | | | | | | | | This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. llvm-svn: 185433
* [XCore] Fix instruction selection for zext, mkmsk instructions.Richard Osborne2013-07-024-2/+20
| | | | | | | | | | | r182680 replaced CountLeadingZeros_32 with a template function countLeadingZeros that relies on using the correct argument type to give the right result. The type passed in the XCore backend after this revision was incorrect in a couple of places. Patch by Robert Lytton. llvm-svn: 185430
* Fix ARM EHABI compact model 1 and 2 without handlerdata.Logan Chien2013-07-022-4/+14
| | | | | | | | | | | | | | According to ARM EHABI section 9.2, if the __aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is used, then the handler data must be emitted after the unwind opcodes. The handler data consists of several words, and should be terminated by zero. In case that the .handlerdata directive is not specified by the programmer, we should emit zero to terminate the handler data. llvm-svn: 185422
* Fixed alignment of code sections in the JIT mode. Added a test to the ↵Elena Demikhovsky2013-07-022-2/+30
| | | | | | JITMemoryManager. llvm-svn: 185421
* DAGCombiner: fix use-counting issue when forming zextloadTim Northover2013-07-022-1/+17
| | | | | | | | | | DAGCombiner was counting all uses of a load node when considering whether it's worth combining into a zextload. Really, it wants to ignore the chain and just count real uses. rdar://problem/13896307 llvm-svn: 185419
* Revert r185257 (InstCombine: Be more agressive optimizing 'udiv' instrs with ↵Hal Finkel2013-07-023-77/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'select' denoms) I'm reverting this commit because: 1. As discussed during review, it needs to be rewritten (to avoid creating and then deleting instructions). 2. This is causing optimizer crashes. Specifically, I'm seeing things like this: While deleting: i1 % Use still stuck around after Def is destroyed: <badref> = select i1 <badref>, i32 0, i32 1 opt: /src/llvm-trunk/lib/IR/Value.cpp:79: virtual llvm::Value::~Value(): Assertion `use_empty() && "Uses remain when a value is destroyed!"' failed. I'd guess that these will go away once we're no longer creating/deleting instructions here, but just in case, I'm adding a regression test. Because the code is bring rewritten, I've just XFAIL'd the original regression test. Original commit message: InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms Real world code sometimes has the denominator of a 'udiv' be a 'select'. LLVM can handle such cases but only when the 'select' operands are symmetric in structure (both select operands are a constant power of two or a left shift, etc.). This falls apart if we are dealt a 'udiv' where the code is not symetric or if the select operands lead us to more select instructions. Instead, we should treat the LHS and each select operand as a distinct divide operation and try to optimize them independently. If we can to simplify each operation, then we can replace the 'udiv' with, say, a 'lshr' that has a new select with a bunch of new operands for the select. llvm-svn: 185415
* Add missing break statements. Noticed by inspection.Nick Lewycky2013-07-021-0/+2
| | | | llvm-svn: 185414
* Fix typo in commentTobias Grosser2013-07-021-1/+1
| | | | llvm-svn: 185413
* Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handlingHal Finkel2013-07-026-35/+331
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of (small) related changes here: 1. The printed name of the VRSAVE register has been changed from VRsave to vrsave in order to match the name accepted by GNU binutils. 2. Support for parsing vrsave has been added to the asm parser (it seems that there was no test case specifically covering this code, so I've added one). 3. The list of Altivec registers, which was common to all calling conventions, has been separated out. This allows us to define the base CSR lists, and then lists for each ABI with Altivec included. This allows SjLj, for example, to work correctly on non-Altivec targets without using unnatural definitions of the NoRegs CSR list. 4. VRSAVE is now always reserved on non-Darwin targets and all Altivec registers are reserved when Altivec is disabled. With these changes, it is now possible to compile a function containing __builtin_unwind_init() on Linux/PPC64 with debugging information. This did not work previously because GNU binutils assumes that all .cfi_offset offsets will be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned offset). This is not true for the vrsave register, however, because this register is used only on Darwin, GCC does not bother printing a .cfi_offset entry for it (even though there is a slot in the stack frame for it as specified by the ABI). This change allows us to do the same: we will also not print .cfi_offset directives for vrsave. llvm-svn: 185409
* IRVerifier: Correctly check attribute typesTobias Grosser2013-07-021-1/+2
| | | | | | | | | | | Add missing parenthesis such that all and not only the very first attribute is checked. Testing this piece of code is not possible with an LLVM-IR test file, as the LLVM-IR parser has a similar check such that the wrong IR does not even arrive at the verifier. llvm-svn: 185408
* [mips] Add new InstrItinClasses for move from/to coprocessor instructions andAkira Hatanaka2013-07-024-56/+70
| | | | | | | | floating point loads and stores. No changes in functionality. llvm-svn: 185399
* PR14728: DebugInfo: TLS variables with -gsplit-dwarfDavid Blaikie2013-07-014-17/+57
| | | | llvm-svn: 185398
* [APFloat] Ensure that we can properly parse strings that do not have null ↵Michael Gottesman2013-07-012-1/+33
| | | | | | | | terminators. rdar://14323230 llvm-svn: 185397
* Fix up some asserts that are within an if statement. This removes the needRichard Trieu2013-07-011-4/+6
| | | | | | for assert(0 && "text"). llvm-svn: 185396
* Tweak some comments that referred to the old bias computations.Jakob Stoklund Olesen2013-07-011-13/+13
| | | | llvm-svn: 185395
* [PowerPC] Add support for TLS data relocationsUlrich Weigand2013-07-017-2/+45
| | | | | | | | | | This adds support for TLS data relocations and modifiers: .quad target@dtpmod .quad target@tprel .quad target@dtprel Currently exploited by the asm parser only. llvm-svn: 185394
* Remove floating point computations form SpillPlacement.cpp.Jakob Stoklund Olesen2013-07-013-69/+70
| | | | | | | | | | | | | | | | | | Patch by Benjamin Kramer! Use the BlockFrequency class instead of floats in the Hopfield network computations. This rescales the node Bias field from a [-2;2] float range to two block frequencies BiasN and BiasP pulling in opposite directions. This construct has a more predictable behavior when block frequencies saturate. The per-node scaling factors are no longer necessary, assuming the block frequencies around a bundle are consistent. This patch can cause the register allocator to make different spilling decisions. The differences should be small. llvm-svn: 185393
* Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...Richard Trieu2013-07-011-7/+5
| | | | llvm-svn: 185392
* [PowerPC] Fix 32-bit PowerPC TLS relocsUlrich Weigand2013-07-012-8/+14
| | | | | | | Some TLS relocs were copied incorrectly from ppc64 to ppc32, and some were missing completely. llvm-svn: 185390
* PR16493: DebugInfo with TLS on PPC crashing due to invalid relocationDavid Blaikie2013-07-017-9/+38
| | | | | | | | Restrict the current TLS support to X86 ELF for now. Test that we don't produce it on PPC & we can flesh that test case out with the right thing once someone implements it. llvm-svn: 185389
* [PowerPC] Support all condition register logical instructionsUlrich Weigand2013-07-013-12/+54
| | | | | | | This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. llvm-svn: 185387
OpenPOWER on IntegriCloud