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* Add MachineInstr::tieOperands, remove setIsTied().Jakob Stoklund Olesen2012-08-314-20/+31
| | | | | | | | | | | Manage tied operands entirely internally to MachineInstr. This makes it possible to change the representation of tied operands, as I will do shortly. The constraint that tied uses and defs must be in the same order was too restrictive. llvm-svn: 163021
* Fix PR12359Michael Liao2012-08-312-3/+15
| | | | | | | | | - In addition to undefined, if V2 is zero vector, skip 2nd PSHUFB and POR as well as PSHUFB will zero elements with negative indices. Patch by Sriram Murali <sriram.murali@intel.com> llvm-svn: 163018
* The instruction DINS may be transformed into DINSU or DEXTM dependingJack Carter2012-08-315-23/+60
| | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 163010
* Move the GCOVFormat enums into their own namespace per the LLVM coding standard.Bill Wendling2012-08-312-24/+26
| | | | llvm-svn: 163008
* Add a comment to explain what's really going on.Chad Rosier2012-08-311-0/+6
| | | | llvm-svn: 163005
* The ConvertToMCInst() function can't fail, so remove the now dead ↵Chad Rosier2012-08-314-9/+0
| | | | | | Match_ConversionFail enum. llvm-svn: 163002
* Mark FMA3 instructions as commutable so that the operands to the multiply ↵Craig Topper2012-08-312-15/+19
| | | | | | part can be commuted. llvm-svn: 163001
* Use CloneMachineInstr to make a new MI in commuteInstruction to make the ↵Craig Topper2012-08-311-10/+1
| | | | | | code tolerant of instructions with more than two input operands. llvm-svn: 163000
* Add support for converting llvm.fma to fma4 instructions.Craig Topper2012-08-315-36/+121
| | | | llvm-svn: 162999
* Don't enforce ordered inline asm operands.Jakob Stoklund Olesen2012-08-312-10/+9
| | | | | | | | | I was too optimistic, inline asm can have tied operands that don't follow the def order. Fixes PR13742. llvm-svn: 162998
* Clean up ProfileDataLoader a bit.Benjamin Kramer2012-08-312-55/+25
| | | | | | | | | | | | - Overloading operator<< for raw_ostream and pointers is dangerous, it alters the behavior of code that includes the header. - Remove unused ID. - Use LLVM's byte swapping helpers instead of a hand-coded. - Make ReadProfilingData work directly on a pointer. No functionality change. llvm-svn: 162992
* llvm/test/CodeGen/X86/vec_select.ll: Fix failure on xmm-less hosts, to add ↵NAKAMURA Takumi2012-08-311-1/+1
| | | | | | | -mattr=+sse2. FIXME: Should this be tested with both +avx and -avx,+sse2? llvm-svn: 162983
* Cleanups due to feedback. No functionality change. Patch by Alistair.Bill Wendling2012-08-313-64/+64
| | | | llvm-svn: 162979
* Clean up AddedComplexity further after adding UseSSExMichael Liao2012-08-311-17/+13
| | | | llvm-svn: 162973
* Fix a couple of typos in EmitAtomic.Jakob Stoklund Olesen2012-08-312-2/+12
| | | | | | | | | Thumb2 instructions are mostly constrained to rGPR, not tGPR which is for Thumb1. rdar://problem/12203728 llvm-svn: 162968
* X86: Fix encoding of 'movd %xmm0, %rax'Jim Grosbach2012-08-312-1/+5
| | | | | | | The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v' prefix, resulting in mis-assembly of the vanilla movd instruction. llvm-svn: 162963
* With the fix in r162954/162955 every cvt function returns true. Thus, haveChad Rosier2012-08-312-77/+53
| | | | | | | the ConvertToMCInst() return void, rather then a bool. Update all the cvt functions as well. llvm-svn: 162961
* Take account of boolean vector contents when promoting a build vector from ↵Pete Cooper2012-08-302-1/+33
| | | | | | i1 to some other type. rdar://problem/12210060 llvm-svn: 162960
* Try to make this test more generic to unbreak buildbots.Owen Anderson2012-08-301-9/+9
| | | | llvm-svn: 162958
* Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by ↵Owen Anderson2012-08-302-1/+159
| | | | | | constants. This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants. llvm-svn: 162956
* Fix for r162954. Return the Error.Chad Rosier2012-08-301-2/+2
| | | | llvm-svn: 162955
* Move a check to the validateInstruction() function where it more properly ↵Chad Rosier2012-08-301-11/+13
| | | | | | belongs. llvm-svn: 162954
* [llvm] Updated the test fold-vector-select so that we test the vector ↵Michael Gottesman2012-08-301-9/+144
| | | | | | selects exhaustively. llvm-svn: 162953
* Typo.Chad Rosier2012-08-301-1/+1
| | | | llvm-svn: 162952
* Whitespace.Chad Rosier2012-08-301-1/+1
| | | | llvm-svn: 162946
* Whitespace.Chad Rosier2012-08-301-1/+1
| | | | llvm-svn: 162945
* Hoist a check to eliminate obvious mismatches as early as possible. Also, fixChad Rosier2012-08-301-8/+8
| | | | | | an 80-column violation in the generated code. No functional change intended. llvm-svn: 162944
* Currently targets that do not support selects with scalar conditions and ↵Nadav Rotem2012-08-302-1/+82
| | | | | | | | | | | vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926
* [ms-inline asm] Add a new function, GetMCInstOperandNum, to theChad Rosier2012-08-301-1/+43
| | | | | | | | | | | | | | | | | | | | | | | AsmMatcherEmitter. This function maps inline assembly operands to MCInst operands. For example, '__asm mov j, eax' is represented by the follow MCInst: <MCInst 1460 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> <MCOperand Expr:(j)> <MCOperand Reg:0> <MCOperand Reg:43>> The first 5 MCInst operands are a result of j matching as a memory operand consisting of a BaseReg (Reg:0), MemScale (Imm:1), MemIndexReg(Reg:0), Expr (Expr:(j), and a MemSegReg (Reg:0). The 6th MCInst operand represents the eax register (Reg:43). This translation is necessary to determine the Input and Output Exprs. If a single asm operand maps to multiple MCInst operands, the index of the first MCInst operand is returned. Ideally, it would return the operand we really care out (i.e., the Expr:(j) in this case), but I haven't found an easy way of doing this yet. llvm-svn: 162920
* Introduce 'UseSSEx' to force SSE legacy encodingMichael Liao2012-08-307-127/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is enabled. As the penalty of inter-mixing SSE and AVX instructions, we need prevent SSE legacy insn from being generated except explicitly specified through some intrinsics. For patterns supported by both SSE and AVX, so far, we force AVX insn will be tried first relying on AddedComplexity or position in td file. It's error-prone and introduces bugs accidentally. 'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited by AVX, we need this predicate to force VEX encoding or SSE legacy encoding only. For insns not inherited by AVX, we still use the previous predicates, i.e. 'HasSSEx'. So far, these insns fall into the following categories: * SSE insns with MMX operands * SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH, CRC, and etc.) * SSE4A insns. * MMX insns. * x87 insns added by SSE. 2 test cases are modified: - test/CodeGen/X86/fast-isel-x86-64.ll AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be selected by fast-isel due to complicated pattern and fast-isel fallback to materialize it from constant pool. - test/CodeGen/X86/widen_load-1.ll AVX code generation is different from SSE one after fixing SSE/AVX inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of 'vmovaps'. llvm-svn: 162919
* ADTTests: [CMake] Exclude DenseMapTest.cpp and SmallVectorTest.cpp on MSVC9 ↵NAKAMURA Takumi2012-08-301-1/+14
| | | | | | due to its bug. llvm-svn: 162918
* Apply "/Og-" also to MSC15(aka VS9) on VMCore/Function.cpp.NAKAMURA Takumi2012-08-301-1/+1
| | | | llvm-svn: 162917
* PPCISelLowering.cpp: Fix r162725.NAKAMURA Takumi2012-08-301-1/+5
| | | | | | | | [Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good! Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good. llvm-svn: 162916
* PPCISelLowering.cpp: Whitespace.NAKAMURA Takumi2012-08-301-1/+1
| | | | llvm-svn: 162915
* testMichael Ilseman2012-08-301-2/+2
| | | | llvm-svn: 162914
* Fix test case.Benjamin Kramer2012-08-301-1/+1
| | | | llvm-svn: 162913
* LoopRotate: Also rotate loops with multiple exits.Benjamin Kramer2012-08-302-13/+260
| | | | | | | | | | | | | | | The old PHI updating code in loop-rotate was replaced with SSAUpdater a while ago, it has no problems with comples PHIs. What had to be fixed is detecting whether a loop was already rotated and updating dominators when multiple exits were present. This change increases overall code size a bit, mostly due to additional loop unrolling opportunities. Passes test-suite and selfhost with -verify-dom-info. Fixes PR7447. Thanks to Andy for the input on the domtree updating code. llvm-svn: 162912
* InstCombine: Fix comment to reflect the code.Benjamin Kramer2012-08-301-1/+1
| | | | llvm-svn: 162911
* Don't use MCInstrDesc flags for implicit operands.Jakob Stoklund Olesen2012-08-301-11/+16
| | | | | | | | | | | | | When a MachineInstr is constructed, its implicit operands are added first, then the explicit operands are inserted before the implicits. MCInstrDesc has oprand flags like early clobber and operand ties that apply to the explicit operands. Don't look at those flags when the implicit operands are first added in the explicit operands's positions. llvm-svn: 162910
* WhitespaceAlexey Samsonov2012-08-301-3/+3
| | | | llvm-svn: 162907
* It is illegal to transform (sdiv (ashr X c1) c2) -> (sdiv x (2^c1 * c2)),Nadav Rotem2012-08-302-35/+0
| | | | | | | | because C always rounds towards zero. Thanks Dirk and Ben. llvm-svn: 162899
* Add support for moving pure S-register to NEON pipeline if desiredTim Northover2012-08-302-2/+135
| | | | llvm-svn: 162898
* remove old docsNadav Rotem2012-08-301-8/+0
| | | | llvm-svn: 162896
* Refactor fetching file/line info from DWARFContext to simplify theAlexey Samsonov2012-08-304-63/+127
| | | | | | | | code and allow better code reuse. Make the code a bit more conforming to LLVM code style. No functionality change. llvm-svn: 162895
* Add FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be ↵Craig Topper2012-08-301-0/+1
| | | | | | expanded when it isn't legal. llvm-svn: 162894
* Add support for FMA to WidenVectorResult.Craig Topper2012-08-302-0/+14
| | | | llvm-svn: 162893
* Only perform DAG combine on FMAs of legal types.Craig Topper2012-08-301-0/+4
| | | | llvm-svn: 162892
* Pass by pointer and not std::string.Bill Wendling2012-08-301-2/+2
| | | | llvm-svn: 162888
* Should put test case under test/ExecutionEngine/MCJIT/Michael Liao2012-08-301-0/+0
| | | | llvm-svn: 162885
* Revert r162855 in favor of changing clang to emit the absolute coverage file ↵Bill Wendling2012-08-301-19/+7
| | | | | | path. llvm-svn: 162883
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