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* [coverity] Fix uninit variable.Vassil Vassilev2017-03-171-1/+1
| | | | | | Patch by John Harvey! llvm-svn: 298122
* AMDGPU: Fix handling of constant phi input loop conditionsMatt Arsenault2017-03-172-5/+266
| | | | | | | | If the loop condition was an i1 phi with a constantexpr input, this would add a loop intrinsic fed by a phi dependent on a call to if.break in the same block. Insert the call in the loop header. llvm-svn: 298121
* [PGO] Change the internal options description. nfc.Rong Xu2017-03-171-3/+5
| | | | llvm-svn: 298120
* AMDGPU: Cleanup control flow intrinsicsMatt Arsenault2017-03-1711-106/+116
| | | | | | | | | | | | | | | | Move backend internal intrinsics along with the rest of the normal intrinsics, and use the Intrinsic::getDeclaration API instead of manually constructing the type list. It's surprising this was working before. fdiv.fast had the wrong number of parameters. The control flow intrinsic declaration attributes were not being applied, and their types were inconsistent. The actual IR use types did not match the declaration, and were closer to the types used for the patterns. The brcond lowering was changing the types, so introduce new nodes for those. llvm-svn: 298119
* [x86] clean up setcc with negated operand transform and add missing test; NFCISanjay Patel2017-03-172-23/+52
| | | | llvm-svn: 298118
* [X86] Emit fewer instructions to allocate >16GB stack framesReid Kleckner2017-03-172-37/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Use this code pattern when RAX is live, instead of emitting up to 2 billion adjustments: pushq %rax movabsq +-$Offset+-8, %rax addq %rsp, %rax xchg %rax, (%rsp) movq (%rsp), %rsp Try to clean this code up a bit while I'm here. In particular, hoist the logic that handles the entire adjustment with `movabsq $imm, %rax` out of the loop. This negates the offset in the prologue and uses ADD because X86 only has a two operand subtract which always subtracts from the destination register, which can no longer be RSP. Fixes PR31962 Reviewers: majnemer, sdardis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30052 llvm-svn: 298116
* [PGO] Add omitted test cases.Rong Xu2017-03-172-0/+158
| | | | llvm-svn: 298115
* [CodeGenPrep]Restructure promoting Ext to form ExtLoadJun Bum Lim2017-03-173-108/+137
| | | | | | | | | | | | | | | | Summary: Instead of just looking for a load which is mergable with Ext to form ExtLoad, trying to promote Exts as long as the cost is acceptable. This change is not a NFC as it continue promoting Exts even after finding a load during promotions; the change in arm64-codegen-prepare-extload.ll described in 2.b might show the case. This change was motivated from D26524. Based on this change, I will move the transformation performed in aarch64-type-promotion into CGP. Reviewers: jmolloy, qcolombet, mcrosier, javed.absar Reviewed By: qcolombet Subscribers: rengolin, llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27853 llvm-svn: 298114
* [PGO] Value profile for size of memory intrinsic callsRong Xu2017-03-173-5/+108
| | | | | | | | This patch annotates the valuesites profile to memory intrinsics. Differential Revision: http://reviews.llvm.org/D31002 llvm-svn: 298110
* [Bitcode] Add compatibility test for the 4.0 releaseVedant Kumar2017-03-172-0/+1689
| | | | | | | Fork off compatibility.ll for the 4.0 release. The *.bc file in this commit was produced using a Release build of the release_40 branch. llvm-svn: 298109
* [SelectionDAG] Add SelectionDAG.computeKnownBits test support for ISD::ABSSimon Pilgrim2017-03-172-10/+22
| | | | llvm-svn: 298108
* [x86] avoid adc/sbb assert when both sides of add are zexted (PR32316)Sanjay Patel2017-03-172-2/+33
| | | | | | | | | | | | | | As noted in the comment, we might want to account for this case, but I didn't look at what that would mean for the asm. I'm also not sure why this only reproduces with avx512, but I'm putting a conservative fix in for now to avoid the crash. Also, if both sides of an add are zexted, shouldn't we shrink that add? https://bugs.llvm.org/show_bug.cgi?id=32316 llvm-svn: 298107
* Fix wasm build after arg_begin iterator type changeReid Kleckner2017-03-171-1/+1
| | | | llvm-svn: 298106
* Store Arguments in a flat array instead of an iplistReid Kleckner2017-03-174-43/+72
| | | | | | | | | | | | | | | | | | | | This saves two pointers from Argument and eliminates some extra allocations. Arguments cannot be inserted or removed from a Function because that would require changing its Type, which LLVM does not allow. Instead, passes that change prototypes, like DeadArgElim, create a new Function and copy over argument names and attributes. The primary benefit of iplist is O(1) random insertion and removal. We just don't need that for arguments, so don't use it. Reviewed By: chandlerc Subscribers: dlj, inglorion, llvm-commits Differential Revision: https://reviews.llvm.org/D31058 llvm-svn: 298105
* Only unswitch loops with uniform conditionsStanislav Mekhanoshin2017-03-177-7/+114
| | | | | | | | | | | | | | | | | | Loop unswitching can be extremely harmful for a SIMT target. In case if hoisted condition is not uniform a SIMT machine will execute both clones of a loop sequentially. Therefor LoopUnswitch checks if the condition is non-divergent. Since DivergenceAnalysis adds an expensive PostDominatorTree analysis not needed for non-SIMT targets a new option is added to avoid unneded analysis initialization. The method getAnalysisUsage is called when TargetTransformInfo is not yet available and we cannot use it here. For that reason a new field DivergentTarget is added to PassManagerBuilder to control the behavior and set this field from a target. Differential Revision: https://reviews.llvm.org/D30796 llvm-svn: 298104
* [X86] Add SelectionDAG.computeKnownBits test showing inability to handle ↵Simon Pilgrim2017-03-171-0/+61
| | | | | | | | ISD::ABS We have to be careful as abs(INT_MIN) == INT_MIN. llvm-svn: 298103
* [AArch64] Use alias analysis in the load/store optimization pass.Chad Rosier2017-03-172-7/+44
| | | | | | | | This allows the optimization to rearrange loads and stores more aggressively. Differential Revision: http://reviews.llvm.org/D30903 llvm-svn: 298092
* [Asm] Don't list '@<type>' in diag when '@' is a commentOliver Stannard2017-03-172-2/+10
| | | | | | | | This fixes https://bugs.llvm.org//show_bug.cgi?id=31280 Differential revision: https://reviews.llvm.org/D31026 llvm-svn: 298067
* [ARM] Fix triple format in test branch disassemble testAndre Vieira2017-03-173-11/+48
| | | | | | | | | | | | Fixing triple format in the tests added for the branch label fix for Thumb Targets. Also recommitting previously approved patch, see https://reviews.llvm.org/D30943. Reviewed by: samparker Differential Revision: https://reviews.llvm.org/D30987 llvm-svn: 298056
* [AVX-512] Make VEX encoded FMA instructions available when AVX512 is enabled ↵Craig Topper2017-03-172-62/+236
| | | | | | | | | | | | regardless of whether +fma was added on the command line. We weren't able to handle isel of the 128/256-bit FMA instructions when AVX512F was enabled but VLX and FMA weren't. I didn't mask FeatureAVX512 imply FeatureFMA as I wasn't sure I wanted disabling FMA to also disable AVX512. Instead we just can't prevent FMA instructions if AVX512 is enabled. Another option would be to promote 128/256-bit to 512-bit, do the operation and extract it. But that requires a lot of extra isel patterns. Since no CPUs exist that support AVX512, but not FMA just using the VEX instructions seems better. llvm-svn: 298051
* [X86] Remove unused predicate. NFCCraig Topper2017-03-171-1/+0
| | | | llvm-svn: 298050
* [SystemZ] New CodeGen tests for vector compare / select.Jonas Paulsson2017-03-172-0/+9162
| | | | | | | | | | New SystemZ tests for the improved codegen of vector compare and select, including cases with a logical combination of two compares. Review: Ulrich Weigand. https://reviews.llvm.org/D29489 llvm-svn: 298049
* Add SystemZ to utils/update_llc_test_checks.py.Jonas Paulsson2017-03-171-0/+18
| | | | | | | | | Extend script for auto-generating CHECK lines so that it works for SystemZ. This is a pre-commit for the new tests resulting from https://reviews.llvm.org/D29489 llvm-svn: 298048
* [SystemZ] Add use of super-reg in splitMove()Jonas Paulsson2017-03-172-1/+427
| | | | | | | | | | | | | | | | | If one of the subregs of the 128 bit reg is undefined when splitMove() splits a store into two instructions, a use of an undefined physical register results. To remedy this, an implicit use of the super register is added onto both new instructions, along with propagated kill and undef flags. This was discovered with llvm-stress, and that test case is attached as test/CodeGen/SystemZ/splitMove_undefReg_mverifier.ll Thanks to Matthias Braun for helping with a nice explanation. Review: Ulrich Weigand llvm-svn: 298047
* [AVX-512] Give priority to EVEX encoded scalar FMA instructions when we have ↵Craig Topper2017-03-172-9/+11
| | | | | | | | FMA, AVX512 and no VLX. We were giving priority if VLX was enabled. llvm-svn: 298046
* [X86] Use update_llc_test_checks.py to regenerate a test and add command ↵Craig Topper2017-03-171-17/+209
| | | | | | | | lines to demonstrate that we don't pick EVEX encoded instruction when AVX512 and FMA3 are both enabled. This bug only exists on the scalar llvm.fma instrinsics. Looks like we don't test the llvm.fma intrinsics very thoroughly. In fact I don't see any tests for the vector versions. llvm-svn: 298045
* [X86] Use update_llc_test_checks.py to regenerate a test.Craig Topper2017-03-171-0/+8
| | | | llvm-svn: 298044
* [X86] Cleanup the AddedComplexity values on move immediate instructions. NFCCraig Topper2017-03-172-8/+10
| | | | | | This makes the values a little more consistent between similar instruction and reduces the values some. This results in better grouping in the isel table saving a few bytes. llvm-svn: 298043
* [libFuzzer] inline the code of __sanitizer_cov_trace_pc_guard into itKostya Serebryany2017-03-172-9/+3
| | | | llvm-svn: 298032
* [libFuzzer] Experimenting with dictionary minimization.Kostya Serebryany2017-03-172-0/+82
| | | | | | | | | | | | | | Summary: Tracking issue: https://github.com/google/oss-fuzz/issues/331 Reviewers: kcc Reviewed By: kcc Differential Revision: https://reviews.llvm.org/D30940 llvm-svn: 298031
* [libFuzzer] add a test with two different bugsKostya Serebryany2017-03-172-0/+23
| | | | llvm-svn: 298030
* [RSForGC] Handle vector GEPsSanjoy Das2017-03-172-0/+20
| | | | | | | | | We were not handling getelemenptr instructions of vector type before. Since getelemenptr instructions for vector types follow the same rule as getelementptr instructions for non-vector types, we can just handle them in the same way. llvm-svn: 298028
* Revert "Make NativeExeSymbol a concrete subclass of NativeRawSymbol [PDB]"Zachary Turner2017-03-177-134/+35
| | | | | | | For some reason this is causing ANSI color codes to be printed even when run through FileCheck. llvm-svn: 298026
* SplitKit: Correctly implement partial subregister copiesMatthias Braun2017-03-174-26/+232
| | | | | | | | | | | - This fixes a bug where subregister incompatible with the vregs register class where used. - Implement the case where multiple copies are necessary to cover a given lanemask. Differential Revision: https://reviews.llvm.org/D30438 llvm-svn: 298025
* VirtRegMap: Correctly deal with bundles when deleting identity copies.Matthias Braun2017-03-173-20/+60
| | | | | | | | | | | | | | | | | | This fixes two problems when VirtRegMap encounters bundles: - When substituting a vreg subregister def with an actual register the internal read flag must be cleared. - Removing an identity COPY from a bundle needs to use removeFromBundle() and a newly introduced function to update SlotIndexes. No testcase here, because none of the in-tree targets trigger this, however an upcoming commit of mine will need this and the testcase there will trigger this. Differential Revision: https://reviews.llvm.org/D30925 llvm-svn: 298024
* Remove LessPreciseFPMADOption from TargetOptions along with all of theEric Christopher2017-03-174-27/+3
| | | | | | | associated command line options and functions - it's currently unused in all of llvm and clang other than being set and reset. llvm-svn: 298023
* [ARM] Use alias analysis in ARMPreAllocLoadStoreOpt.Eli Friedman2017-03-173-16/+72
| | | | | | | | | | This allows the optimization to rearrange loads and stores more aggressively. This doesn't really affect performance, but it helps codesize. Differential Revision: https://reviews.llvm.org/D30839 llvm-svn: 298021
* LTO: Fix a potential race condition in the caching API.Peter Collingbourne2017-03-174-22/+41
| | | | | | | | | | | | | | | | | | | | | After the call to sys::fs::exists succeeds, indicating a cache hit, we call AddFile and the client will open the file using the supplied path. If the client is using cache pruning, there is a potential race between the pruner and the client. To avoid this, change the caching API so that it provides a MemoryBuffer to the client, and have clients use that MemoryBuffer where possible. This scheme won't work with the gold plugin because the plugin API expects a file path. So we have the gold plugin use the buffer identifier as a path and live with the race for now. (Note that the gold plugin isn't actually affected by the problem at the moment because it doesn't support cache pruning.) This effectively reverts r279883 modulo the change to use the existing path in the gold plugin. Differential Revision: https://reviews.llvm.org/D31063 llvm-svn: 298020
* SmallString doesn't have implicit conversion from const char*.Zachary Turner2017-03-171-2/+2
| | | | llvm-svn: 298019
* Don't rely on an implicit std::tuple constructor.Zachary Turner2017-03-171-4/+9
| | | | | | | Apparently it doesn't have one, so using an initializer list doesn't work correctly. llvm-svn: 298018
* [pdb] Fix an uninitialized read, and add a test for it.Zachary Turner2017-03-173-6/+32
| | | | | | | | | | | | | | | | | | | This was originally reported in pr32249, uncovered by PTVS-Studio. There was no code coverage for this path because it was difficult to construct odd-case PDB files that were not generated by cl. Now that we can write construct minimal PDB files from YAML, it's easy to construct fragments that generate whatever we want. In this patch I add a test that creates 2 type records. One with a unique name, and one without. I verify that we can go from PDB to Yaml with no errors. In a future patch I'd like to add something like llvm-pdbdump raw -lookup-type that will just dump one record and nothing else, which should make it a bit cleaner to find this kind of thing. llvm-svn: 298017
* [PDB] It is not an error getting the "Invalid" Annotation opcode.Zachary Turner2017-03-171-2/+2
| | | | | | | The linker can insert invalid opcodes to indicate padding bytes, and we should not fail in this case. llvm-svn: 298016
* clean Lanai namespaceJacques Pienaar2017-03-162-4/+4
| | | | | | | | | | | | | | Summary: This patch cleans the namespace of the Lanai target. Reviewers: jpienaar Reviewed By: jpienaar Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30955 llvm-svn: 298015
* Fix unit test.Zachary Turner2017-03-161-1/+1
| | | | llvm-svn: 298014
* Remove getArgumentList() in favor of arg_begin(), args(), etcReid Kleckner2017-03-1615-40/+28
| | | | | | | | | | | | | | | | | Users often call getArgumentList().size(), which is a linear way to get the number of function arguments. arg_size(), on the other hand, is constant time. In general, the fact that arguments are stored in an iplist is an implementation detail, so I've removed it from the Function interface and moved all other users to the argument container APIs (arg_begin(), arg_end(), args(), arg_size()). Reviewed By: chandlerc Differential Revision: https://reviews.llvm.org/D31052 llvm-svn: 298010
* Remove dead F parameter from Argument constructorReid Kleckner2017-03-162-11/+5
| | | | | | | | When Function creates its argument list, it does the ilist push_back itself. No other caller passes in a parent function, so this is dead, and it uses the soon-to-be-deleted getArgumentList accessor. llvm-svn: 298009
* Fix linux build.Zachary Turner2017-03-161-1/+2
| | | | llvm-svn: 298007
* Make NativeExeSymbol a concrete subclass of NativeRawSymbol [PDB]Adrian McCarthy2017-03-167-35/+134
| | | | | | | | | | | This moves exe symbol-specific method implementations out of NativeRawSymbol into a concrete subclass. Also adds implementations for hasCTypes and hasPrivateSymbols and a simple test to ensure the native reader can access the summary information for the executable from the PDB. Differential Revision: https://reviews.llvm.org/D31059 llvm-svn: 298005
* [Support] Support both Windows and Posix paths on both platforms.Zachary Turner2017-03-164-346/+316
| | | | | | | | | | | | | | | | | | Previously which path syntax we supported dependend on what platform we were compiling LLVM on. While this is normally desirable, there are situations where we need to be able to handle a path that we know was generated on a remote host. Remote debugging, for example, or parsing debug info. 99% of the code in LLVM for handling paths was platform agnostic and literally just a few branches were gated behind pre-processor checks, so this changes those sites to use runtime checks instead, and adds a flag to every path API that allows one to override the host native syntax. Differential Revision: https://reviews.llvm.org/D30858 llvm-svn: 298004
* Make Argument::getArgNo() constant time, not O(#args)Reid Kleckner2017-03-162-17/+8
| | | | | | | | | | | | | | | | | | | | | | | | getArgNo is actually hot in LLVM, because its how we check for attributes on arguments: bool Argument::hasNonNullAttr() const { if (!getType()->isPointerTy()) return false; if (getParent()->getAttributes(). hasAttribute(getArgNo()+1, Attribute::NonNull)) return true; It actually shows up as the 23rd hottest leaf function in a 13s sample of LTO of llc. This grows Argument by four bytes, but I have another pending patch to shrink it by removing its ilist_node base. Reviewed By: chandlerc Subscribers: inglorion, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D31057 llvm-svn: 298003
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