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* Delete trailing whitespace.Matt Arsenault2014-06-121-1/+1
| | | | | | Hopefully this forces cmake to re-run. llvm-svn: 210830
* Update test case to use "not" instead of "XFAIL".Juergen Ributzka2014-06-121-2/+1
| | | | llvm-svn: 210829
* GVN: Enable value forwarding for callocDuncan P. N. Exon Smith2014-06-122-0/+41
| | | | | | | | | | | | | | | | | | | | | Enable value forwarding for loads from `calloc()` without an intervening store. This change extends GVN to handle the following case: %1 = tail call noalias i8* @calloc(i64 1, i64 4) %2 = bitcast i8* %1 to i32* ; This load is trivially constant zero %3 = load i32* %2, align 4 This is analogous to the handling for `malloc()` in the same places. `malloc()` returns `undef`; `calloc()` returns a zero value. Note that it is correct to return zero even for out of bounds GEPs since the result of such a GEP would be undefined. Patch by Philip Reames! llvm-svn: 210828
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-129-250/+54
| | | | | | | | | Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
* Move DataLayout from the PPCTargetMachine to the subtarget.Eric Christopher2014-06-124-40/+46
| | | | llvm-svn: 210824
* Move PPCFrameLowering into PPCSubtarget from PPCTargetMachine. UseEric Christopher2014-06-126-196/+211
| | | | | | | | the initializeSubtargetDependencies code to obtain an initialized subtarget and migrate a couple of subtarget using functions to the .cpp file to avoid circular includes. llvm-svn: 210822
* LangRef: clarify that global declarations can have section and alignment info.Bob Wilson2014-06-121-4/+6
| | | | | | | | I'm not sure what it means to set a section for a declaration in another translation unit, but there are some tests in the tree that do it so it seems to be legal now regardless. llvm-svn: 210819
* [FastISel][X86] Argument lowering test caseJuergen Ributzka2014-06-121-0/+10
| | | | | | | This test case is supposed to xfail, because we do not handle structs or byval arguments. llvm-svn: 210816
* [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.Juergen Ributzka2014-06-122-20/+65
| | | | | | | Recommit with fixed argument attribute checking code, which is required to bail out of all the cases we don't handle yet. llvm-svn: 210815
* CodeGen: enable mov.w/mov.t pairs with minsize for WoASaleem Abdulrasool2014-06-122-1/+22
| | | | | | | | | Windows on ARM uses COFF/PE which is intrinsically position independent. For the case of 32-bit immediates, use a pair-wise relocation as otherwise we may exceed the range of operators. This fixes a code generation crash when using -Oz when targeting Windows on ARM. llvm-svn: 210814
* Revert "[FastIsel][X86] Add support for lowering the first 8 floating-point ↵Juergen Ributzka2014-06-122-60/+19
| | | | | | | | arguments." Reverting it because it breaks several tests. llvm-svn: 210810
* [llvm-symbolizer] Fix parsing DW_AT_ranges in Fission skeleton compile unit ↵Alexey Samsonov2014-06-124-3/+30
| | | | | | | | | | | | | DIEs. Turns out that DW_AT_ranges_base attribute sets the offset for DW_AT_ranges values specified in the .dwo file, but not for DW_AT_ranges specified in the skeleton compile unit DIE in the main executable. This is extremely confusing, and would hopefully be fixed in DWARF-5 when it's finalized. For now this behavior makes sense, as otherwise Fission would break DWARF consumers who doesn't know anything about DW_AT_ranges_base. llvm-svn: 210809
* Add missing "InitializerConstant" to global variable syntax in LangRef.Bob Wilson2014-06-121-2/+2
| | | | | | | | | | The syntax for Global Variables in LangRef is missing the initializer. This syntax section was added in r199218 along with changes to the dllexport/dllimport handling, and I guess it was just an oversight to omit the initializer values. I’ve marked the initializer as optional because this syntax is used for both declarations and definitions. llvm-svn: 210808
* Revert r210721 as it causes breakage in internal builds (and possibly GDB).Eli Bendersky2014-06-122-394/+6
| | | | llvm-svn: 210807
* X86: stifle GCC warningSaleem Abdulrasool2014-06-121-1/+3
| | | | | | | | | | lib/Target/X86/X86TargetTransformInfo.cpp: In member function ‘virtual unsigned int {anonymous}::X86TTI::getIntImmCost(unsigned int, unsigned int, const llvm::APInt&, llvm::Type*) const’: lib/Target/X86/X86TargetTransformInfo.cpp:920:60: warning: enumeral and non-enumeral type in conditional expression [enabled by default] This seems like an unhelpful warning, but there doesnt seem to be a controlling flag, so add an explicit cast to silence the warning. llvm-svn: 210806
* Trying to fix the windows build.Rafael Espindola2014-06-121-4/+3
| | | | llvm-svn: 210805
* Remove system_error.h.Rafael Espindola2014-06-1258-91/+73
| | | | | | | This is a minimal change to remove the header. I will remove the occurrences of "using std::error_code" in a followup patch. llvm-svn: 210803
* adding re-include guards into lib/Support/reg*.hArtyom Skrobov2014-06-124-0/+20
| | | | llvm-svn: 210794
* Remove pimpl class from PassRegistry.Zachary Turner2014-06-125-216/+198
| | | | | | | | | | | | | | | | | | | Since removeRegistrationListener is no longer called during static destruction, we can get rid of the pimpl in PassRegistry. This should clean up the code somewhat, increase clarity, and also allows us to put the Lock as a member of the class, instead of as a ManagedStatic. As part of this change, the PassInfo class is moved from PassSupport.h to its own file, to eliminate the otherwise circular header dependency between PassRegistry.h and PassSupport.h Reviewed by: rnk, dblaikie Differential Revision: http://reviews.llvm.org/D4107 llvm-svn: 210793
* Revert "SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, ↵Tom Stellard2014-06-123-4/+52
| | | | | | | | | y)) for vectors" This reverts commit r210540, adds a testcase for the regression it caused, and marks the R600 test it was supposed to fix as XFAIL. llvm-svn: 210792
* Disable the load/store optimization pass for Thumb-1.James Molloy2014-06-125-7/+13
| | | | | | | | Moritz's changes have improved codegen a lot, but further testing showed significant correctness problems. Disable by default until these have been worked out. Patch by Moritz Roth! llvm-svn: 210789
* [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-1224-76/+285
| | | | | | | | | | | | | | | | | | | | Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
* [mips][mips64r6] bc2[ft] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-125-2/+28
| | | | | | | | | | | | | | | | Summary: These instructions are not implemented for any MIPS ISA so we only need testcases. Depends on D4110 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4111 llvm-svn: 210786
* [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-1211-210/+454
| | | | | | | | | | | | | | | | | Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
* Replace llvm::error_code with std::error_code.Rafael Espindola2014-06-125-12/+12
| | | | llvm-svn: 210783
* This removes TODO added in http://reviews.llvm.org/D3658Dinesh Dwivedi2014-06-122-2/+489
| | | | | | | | | | | The patch transforms ABS(NABS(X)) -> ABS(X) NABS(ABS(X)) -> NABS(X) Differential Revision: http://reviews.llvm.org/D4040 llvm-svn: 210782
* [mips][mips64r6] prefx is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-123-1/+42
| | | | | | | | | | | | Summary: We haven't implemented this instruction so we only add a test case. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D4004 llvm-svn: 210779
* [mips][mips64r6] 80 col corrections that should have been in r210777.Daniel Sanders2014-06-121-10/+20
| | | | llvm-svn: 210778
* [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available ↵Daniel Sanders2014-06-1221-387/+2775
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
* [mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-123-4/+36
| | | | | | | | | | | | Summary: Depends on D3957 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3958 llvm-svn: 210775
* [mips][mips64r6] Add R_MIPS_PC19_S2Zoran Jovanovic2014-06-127-16/+72
| | | | | | Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
* Don't import make_error_code into the llvm namespace.Rafael Espindola2014-06-128-12/+12
| | | | llvm-svn: 210772
* [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-06-129-34/+63
| | | | | | | | | | | | | | | | | | | | | | FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771
* [mips][mips64r6] Add bgec and bgeuc instructionsZoran Jovanovic2014-06-126-6/+76
| | | | | | Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
* [X86] Teach how to dump the name of target node RDTSCP_DAG.Andrea Di Biagio2014-06-121-0/+1
| | | | | | | | | When I originally added node RDTSCP_DAG (r207127) I forgot to add a string name for it in method 'getTargetNodeName'. No functional change intended. llvm-svn: 210769
* CMake: don't install the internal config.h headerAlp Toker2014-06-121-0/+1
| | | | | | | Background: http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-June/073707.html llvm-svn: 210766
* [mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not ↵Daniel Sanders2014-06-125-45/+322
| | | | | | | | | | | | | | | | | | | | available on MIPS32r6/MIPS64r6 Summary: This patch updates both the assembler and the code generator. MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted. Depends on D3955 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3956 llvm-svn: 210763
* [mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-126-26/+261
| | | | | | | | | | | | | | | | Summary: This patch disables madd/maddu/msub/msubu in both the assembler and code generator. Depends on D3896 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3955 llvm-svn: 210762
* [X86] Teach how to combine AVX and AVX2 horizontal binop on packed 256-bit ↵Andrea Di Biagio2014-06-122-9/+380
| | | | | | | | | | | vectors. This patch adds target combine rules to match: - [AVX] Horizontal add/sub of packed single/double precision floating point values from 256-bit vectors; - [AVX2] Horizontal add/sub of packed integer values from 256-bit vectors. llvm-svn: 210761
* [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ↵Daniel Sanders2014-06-1216-102/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
* [mips] Move CHECK lines to the same line as the instruction it's testingMatheus Almeida2014-06-122-8/+4
| | | | | | | | for consistency with the other tests. No functional changes. llvm-svn: 210757
* R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*Matt Arsenault2014-06-124-47/+51
| | | | | | | There is not such thing as a 0-data ds instruction, and the data operand needs to be a vgpr set to something meaningful. llvm-svn: 210756
* Avoid in-class initializer from r210747Alp Toker2014-06-121-1/+2
| | | | | | Turns out MSVC doesn't like this. Sorry for the noise! llvm-svn: 210749
* Avoid anonymous namespace in header from r210747Alp Toker2014-06-121-13/+11
| | | | llvm-svn: 210748
* Avoid redundant allocations in the linker optimisation hintAlp Toker2014-06-121-2/+14
| | | | llvm-svn: 210747
* [FastISel][x86] Add testcase for r210719.Juergen Ributzka2014-06-121-0/+24
| | | | llvm-svn: 210746
* [x86] Improve frameaddress test from r210709.Juergen Ributzka2014-06-121-10/+27
| | | | llvm-svn: 210743
* [FastISel] Add support for the stackmap intrinsic.Juergen Ributzka2014-06-123-0/+271
| | | | | | This implements target-independent FastISel lowering for the stackmap intrinsic. llvm-svn: 210742
* Prefix generic_category with std::.Rafael Espindola2014-06-121-2/+2
| | | | | | Sorry I missed these before. llvm-svn: 210740
* Don't put generic_category in the llvm namespace.Rafael Espindola2014-06-126-31/+30
| | | | llvm-svn: 210737
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