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* Don't allow TargetFlags on MO_Register MachineOperands.Jakob Stoklund Olesen2012-08-282-10/+21
| | | | | | | | | | | | Register operands are manipulated by a lot of target-independent code, and it is not always possible to preserve target flags. That means it is not safe to use target flags on register operands. None of the targets in the tree are using register operand target flags. External targets should be using immediate operands to annotate instructions with operand modifiers. llvm-svn: 162770
* Patch by Sean Silva to un-barf his computer by explicitly removing the '\n'Bill Wendling2012-08-281-3/+2
| | | | | | character instead of always the last character. llvm-svn: 162767
* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-2810-2/+653
| | | | | | | | | Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. llvm-svn: 162764
* InstCombine: Defensively avoid undefined shifts by limiting the amount to ↵Benjamin Kramer2012-08-281-2/+2
| | | | | | | | | the bit width. No test case, undefined shifts get folded early, but can occur when other transforms generate a constant. Thanks to Duncan for bringing this up. llvm-svn: 162755
* InstCombine: Guard the transform introduced in r162743 against large ints ↵Benjamin Kramer2012-08-282-12/+37
| | | | | | and non-const shifts. llvm-svn: 162751
* Make sure that we don't call getZExtValue on values > 64 bits.Nadav Rotem2012-08-282-8/+15
| | | | | | Thanks Benjamin for noticing this. llvm-svn: 162749
* Teach InstCombine to canonicalize [SU]div+[AL]shl patterns.Nadav Rotem2012-08-283-2/+72
| | | | | | | | | | For example: %1 = lshr i32 %x, 2 %2 = udiv i32 %1, 100 rdar://12182093 llvm-svn: 162743
* The commutative flag is already correctly set within the multiclass. If we setBill Wendling2012-08-282-1/+21
| | | | | | | | it here, then a 'register-memory' version would wrongly get the commutative flag. <rdar://problem/12180135> llvm-svn: 162741
* Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper2012-08-283-18/+10
| | | | llvm-svn: 162740
* Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper2012-08-284-32/+19
| | | | llvm-svn: 162738
* llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.NAKAMURA Takumi2012-08-281-2/+2
| | | | llvm-svn: 162736
* Fix PR12312Michael Liao2012-08-282-10/+160
| | | | | | | | | | - Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. llvm-svn: 162735
* Check all patterns for missing instruction flags.Jakob Stoklund Olesen2012-08-282-0/+72
| | | | | | | Both single-instruction and multi-instruction patterns can be checked for missing mayLoad / mayStore, and hasSideEffects flags. llvm-svn: 162734
* Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen2012-08-285-31/+25
| | | | | | | | | | | | | | | These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. llvm-svn: 162733
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen2012-08-286-169/+43
| | | | | | | | | | | ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
* Fix mips' long branch pass.Akira Hatanaka2012-08-283-109/+141
| | | | | | | | Instructions emitted to compute branch offsets now use immediate operands instead of symbolic labels. This change was needed because there were problems when R_MIPS_HI16/LO16 relocations were used to make shared objects. llvm-svn: 162731
* Split several PPC instruction classes.Hal Finkel2012-08-289-102/+269
| | | | | | | | | | | | | Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. llvm-svn: 162729
* Fix bug 13532.Akira Hatanaka2012-08-282-1/+13
| | | | | | | | | In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without using any f64 operations if f64 is not a legal type. Patch by Stefan Kristiansson. llvm-svn: 162728
* Allow remat of LI on PPC.Hal Finkel2012-08-284-3/+21
| | | | | | | | | | | Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. llvm-svn: 162727
* Add the Freescale vendor to Triple.Hal Finkel2012-08-282-1/+4
| | | | | | | | | Adds the vendor 'fsl' (used by Freescale SDK) to Triple. This will allow clang support for Freescale cross-compile configurations. Patch by Tobias von Koch. llvm-svn: 162726
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-284-8/+60
| | | | | | | | | | | | | | | | The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. llvm-svn: 162725
* Optimize zext on PPC64.Hal Finkel2012-08-282-0/+20
| | | | | | | | | | The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. llvm-svn: 162724
* Temporarily revert this to bring back the bots.Eric Christopher2012-08-284-21/+15
| | | | llvm-svn: 162722
* More missing mayLoad flags on AVX multiclasses.Jakob Stoklund Olesen2012-08-281-3/+3
| | | | llvm-svn: 162714
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-276-43/+169
| | | | | | | | | | | It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. llvm-svn: 162713
* Add --program-prefix support to build.Sebastian Pop2012-08-274-15/+21
| | | | llvm-svn: 162707
* Fix compile error when building with C++11 - clang thinks that PRIx64 is a ↵Marshall Clow2012-08-271-2/+2
| | | | | | user-defined suffix or something llvm-svn: 162704
* Make sure we add the predicate after all of the registers are added.Bill Wendling2012-08-272-2/+132
| | | | | | <rdar://problem/12183003> llvm-svn: 162703
* Don't use for loops for code that is only intended to execute once. NoDan Gohman2012-08-271-6/+6
| | | | | | intended functionality change. Thanks to Ahmed Charles for spotting it. llvm-svn: 162686
* Fix comment.Rafael Espindola2012-08-271-3/+4
| | | | llvm-svn: 162678
* Fix comment for function RuntimeDyldImpl.resolveRelocation()Danil Malyshev2012-08-271-1/+4
| | | | llvm-svn: 162677
* Remove the the block_node_iterator of Region, replace it by the block_iterator.Hongbin Zheng2012-08-273-45/+5
| | | | llvm-svn: 162672
* Support MIPS DSP Rev2 intrinsics.Simon Atanasyan2012-08-271-0/+125
| | | | | | The patch reviewed by Akira Hatanaka. llvm-svn: 162668
* llvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on ↵NAKAMURA Takumi2012-08-271-2/+2
| | | | | | non-x86 hosts. llvm-svn: 162667
* DWARFDebugRangeList.cpp: Use PRIx64 for uint64_t as format string.NAKAMURA Takumi2012-08-271-2/+3
| | | | llvm-svn: 162665
* llvm/test/CodeGen/X86/fma_patterns.ll: Add -mtriple=x86_64. It was ↵NAKAMURA Takumi2012-08-271-1/+1
| | | | | | incompatible on i686 and Windows x64. llvm-svn: 162664
* Remove MMX shift intrinsic handling code that also exists in ↵Craig Topper2012-08-271-56/+0
| | | | | | SelectionDAGBuilder. llvm-svn: 162661
* Commit test change for r162658.Craig Topper2012-08-271-44/+0
| | | | llvm-svn: 162660
* [DebugInfo] fixup for r162657: update CMakeLists.txtAlexey Samsonov2012-08-271-0/+1
| | | | llvm-svn: 162659
* Don't allow vextractf128 to be folded with unaligned stores. We don't fold ↵Craig Topper2012-08-271-13/+9
| | | | | | unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur. llvm-svn: 162658
* Add basic support for .debug_ranges section to LLVM's DebugInfo library.Alexey Samsonov2012-08-278-7/+153
| | | | | | | | | | | This section (introduced in DWARF-3) is used to define instruction address ranges for functions that are not contiguous and can't be described by low_pc/high_pc attributes (this is the usual case for inlined subroutines). The patch is the first step to support fetching complete inlining info from DWARF. Reviewed by Benjamin Kramer. llvm-svn: 162657
* Fold some patterns into instruction definitons so tablegen can infer flags ↵Craig Topper2012-08-271-4/+4
| | | | | | removing the need for an explicit 'neverHasSideEffects = 1' llvm-svn: 162656
* FMA3 tests on bdver2 target for changes made in rev 162012. Also madeAnitha Boyapati2012-08-274-7/+12
| | | | | | | corresponding changes to existing tests for darwin triple to ensure that same pattern is tested for bdver2 target. llvm-svn: 162655
* Add HasAVX1Only predicate and use it for patterns that have an AVX1 ↵Craig Topper2012-08-272-48/+62
| | | | | | instruction and an AVX2 instruction rather than relying on AddedComplexity. llvm-svn: 162654
* Make sure that FMA3 is favored even when FMA4 is also enabled. Test case for ↵Craig Topper2012-08-271-1/+2
| | | | | | r162454. llvm-svn: 162653
* Pass -lLTO after gold-plugin.o so that it gets used in systems that default toRafael Espindola2012-08-271-1/+3
| | | | | | | --as-needed. Patch by Felix Geyer. Fixes pr13262. llvm-svn: 162652
* Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ↵Craig Topper2012-08-261-18/+30
| | | | | | ReadArgMem. llvm-svn: 162649
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-2419-56/+59
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Add missing mayLoad flags to a large class of AVX *_Int instructions.Jakob Stoklund Olesen2012-08-241-1/+2
| | | | llvm-svn: 162622
* Missed tLEApcrelJT.Jakob Stoklund Olesen2012-08-241-0/+1
| | | | | | | ARMConstantIslandPass expects this instruction to stay in the same basic block as the jump table branch. llvm-svn: 162615
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