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* [codeview] Add support for label type recordsReid Kleckner2017-04-0310-1/+66
| | | | | | MASM can produce these type records. llvm-svn: 299388
* [X86][SSE]] Lower BUILD_VECTOR with repeated elts as BUILD_VECTOR + ↵Simon Pilgrim2017-04-0312-103/+142
| | | | | | | | | | | | | | | | VECTOR_SHUFFLE It can be costly to transfer from the gprs to the xmm registers and can prevent loads merging. This patch splits vXi16/vXi32/vXi64 BUILD_VECTORS that use the same operand in multiple elements into a BUILD_VECTOR with only a single insertion of each of those elements and then performs an unary shuffle to duplicate the values. There are a couple of minor regressions this patch unearths due to some missing MOVDDUP/BROADCAST folds that I will address in a future patch. Note: Now that vector shuffle lowering and combining is pretty good we should be reusing that instead of duplicating so much in LowerBUILD_VECTOR - this is the first of several patches to address this. Differential Revision: https://reviews.llvm.org/D31373 llvm-svn: 299387
* [InstCombine] Remove canonicalization for (X & C1) | C2 --> (X | C2) & ↵Craig Topper2017-04-031-11/+0
| | | | | | | | | | (C1|C2) when C1 & C2 have common bits. It turns out that SimplifyDemandedInstructionBits will get called earlier and remove bits from C1 first. Effectively doing (X & (C1&C2)) | C2. So by the time it got to this check there could be no common bits. I think the DAGCombiner has the same check but its check can be executed because it handles demanded bits later. I'll look at it next. llvm-svn: 299384
* x86 interrupt calling convention: re-align stack pointer on 64-bit if an ↵Amjad Aboud2017-04-034-10/+30
| | | | | | | | | | | | | | | | error code was pushed The x86_64 ABI requires that the stack is 16 byte aligned on function calls. Thus, the 8-byte error code, which is pushed by the CPU for certain exceptions, leads to a misaligned stack. This results in bugs such as Bug 26413, where misaligned movaps instructions are generated. This commit fixes the misalignment by adjusting the stack pointer in these cases. The adjustment is done at the beginning of the prologue generation by subtracting another 8 bytes from the stack pointer. These additional bytes are popped again in the function epilogue. Fixes Bug 26413 Patch by Philipp Oppermann. Differential Revision: https://reviews.llvm.org/D30049 llvm-svn: 299383
* [CodeGenPrep] move aarch64-type-promotion to CGPJun Bum Lim2017-04-039-58/+374
| | | | | | | | | | | | | | | | | Summary: Move the aarch64-type-promotion pass within the existing type promotion framework in CGP. This change also support forking sexts when a new sext is required for promotion. Note that change is based on D27853 and I am submitting this out early to provide a better idea on D27853. Reviewers: jmolloy, mcrosier, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: llvm-commits, aemerson, rengolin, mcrosier Differential Revision: https://reviews.llvm.org/D28680 llvm-svn: 299379
* [DAGCombine][InstCombine] Fix inverted if condition in equivalent comments ↵Craig Topper2017-04-032-2/+2
| | | | | | in DAGCombine and InstCombine. NFC llvm-svn: 299378
* Fix LLVMBuild.txt typo. NFCJoel Jones2017-04-031-1/+1
| | | | llvm-svn: 299373
* AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault2017-04-0310-1252/+159
| | | | llvm-svn: 299372
* [Support] Make printAllJSONValues public, for custom output.Graydon Hoare2017-04-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This changes the static method TimerGroup::printAllJSONValues from private to public, to match the static method TimerGroup::printAll. When trying to drive the reporting machinery by hand, the existing API is _almost_ flexible enough, but this entrypoint is required to intermix printing timers with other non-timer output. The underlying motive here is a Swift change to consolidate the collection of timers, LLVM statistics and other (non-assert-dependent) counters into JSON files, which requires a bit of manual intervention in LLVM's stat and timer output routines. See https://github.com/apple/swift/pull/8477 for details. Reviewers: MatzeB Reviewed By: MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31566 llvm-svn: 299371
* Bitcode: Remove reader support for MODULE_CODE_PURGEVALS.Peter Collingbourne2017-04-034-21/+0
| | | | | | | | | | Support for writing this module code was removed in r73220, which was well before the LLVM 3.0 release, so we do not need to be able to understand it for backwards compatibility. Differential Revision: https://reviews.llvm.org/D31563 llvm-svn: 299370
* [InstCombine] Add test cases showing how we fail to fold vector constants ↵Craig Topper2017-04-033-0/+53
| | | | | | into selects the way we do with scalars. llvm-svn: 299369
* Revert "[DAGCombine] A shuffle of a splat is always the splat itself"Zvi Rackover2017-04-032-12/+10
| | | | | | | | | | This reverts commit r299047 which is incorrect because the simplification may result in incorrect propogation of undefs to users of the folded shuffle. Thanks to Andrea Di Biagio for pointing this out. llvm-svn: 299368
* [Hexagon] Factor out some common code in HexagonEarlyIfConv.cpp, NFCKrzysztof Parzyszek2017-04-031-12/+10
| | | | llvm-svn: 299367
* Revert r299337 "[InstCombine] Remove redundant combine from visitAnd"Craig Topper2017-04-032-0/+89
| | | | | | | | One of the tsan bots started failing at this commit. I don't see anything obviously wrong with the commit so trying this to see if it recovers. Failing log: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/6792 llvm-svn: 299366
* [InstCombine] fix formatting for foldLogOpOfMaskedICmps and related bits; NFCISanjay Patel2017-04-031-145/+158
| | | | | | | | | | | | 1. Improve enum, function, and variable names. 2. Improve comments. 3. Fix variable capitalization. 4. Run clang-format. As an existing code comment suggests, this should work with vector types / splat constants too, so making this look right first will reduce the diffs needed for that change. llvm-svn: 299365
* [APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt ↵Craig Topper2017-04-038-43/+54
| | | | | | | | | | class. Implement them without memory allocation for multiword This moves the isMask and isShiftedMask functions to be class methods. They now use the MathExtras.h function for single word size and leading/trailing zeros/ones or countPopulation for the multiword size. The previous implementation made multiple temorary memory allocations to do the bitwise arithmetic operations to match the MathExtras.h implementation. Differential Revision: https://reviews.llvm.org/D31565 llvm-svn: 299362
* [DAGCombiner] Check limits before accessing array element (PR32502)Simon Pilgrim2017-04-031-1/+1
| | | | llvm-svn: 299361
* ARMAsmParser: clean up of isImmediate functionsSjoerd Meijer2017-04-0314-282/+193
| | | | | | | | | | | | | | | | | - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
* [InstCombine] Make foldOpWithConstantIntoOperand take a BinaryOperator ↵Craig Topper2017-04-032-2/+2
| | | | | | | | instead of a generic Instruction. It blindly assumes there are two operands so make it explicit. llvm-svn: 299351
* [InstCombine] Remove a And transform that should be handled by ↵Craig Topper2017-04-031-7/+0
| | | | | | SimplifyDemandedInstructionBits. NFCI llvm-svn: 299349
* Trailing whitespace.NAKAMURA Takumi2017-04-027-8/+8
| | | | llvm-svn: 299344
* Reformat.NAKAMURA Takumi2017-04-022-6/+6
| | | | llvm-svn: 299343
* [APInt] Make use of whichWord and maskBit to simplify some code. NFCCraig Topper2017-04-021-5/+3
| | | | llvm-svn: 299342
* [APInt] Add a public typedef for the internal type of APInt use it instead ↵Craig Topper2017-04-025-167/+169
| | | | | | | | | | | | | | | | of integerPart. Make APINT_BITS_PER_WORD and APINT_WORD_SIZE public. This patch is one step to attempt to unify the main APInt interface and the tc functions used by APFloat. This patch adds a WordType to APInt and uses that in all the tc functions. I've added temporary typedefs to APFloat to alias it to integerPart to keep the patch size down. I'll work on removing that in a future patch. In future patches I hope to reuse the tc functions to implement some of the main APInt functionality. I may remove APINT_ from BITS_PER_WORD and WORD_SIZE constants so that we don't have the repetitive APInt::APINT_ externally. Differential Revision: https://reviews.llvm.org/D31523 llvm-svn: 299341
* [InstCombine] Make InstCombiner::OptAndOp take a BinaryOperator instead of ↵Craig Topper2017-04-022-4/+4
| | | | | | | | | | an Instruction. The callers have already performed the necessary cast before calling. This allows us to remove a comment that says the instruction must be a BinaryOperator and make it explicit in the argument type. Had to add a default case to the switch because BinaryOperator::getOpcode() returns a BinaryOps enum. llvm-svn: 299339
* [X86][MMX] Improve support for folding fptosi from XMM to MMXSimon Pilgrim2017-04-022-7/+13
| | | | llvm-svn: 299338
* [InstCombine] Remove redundant combine from visitAndCraig Topper2017-04-022-89/+0
| | | | | | | | | | As far as I can tell this combine is fully handled by SimplifyDemandedInstructionBits. I was only looking at this because it is the only user of APIntOps::isShiftedMask which is itself broken. As demonstrated by r299187. I was going to fix isShiftedMask and needed to make sure we had coverage for the new cases it would expose to this combine. But looks like we can nuke it instead. Differential Revision: https://reviews.llvm.org/D31543 llvm-svn: 299337
* [X86][MMX] Simplify tablegen patterns by always combining MOVDQ2Q from v2i64Simon Pilgrim2017-04-022-5/+4
| | | | llvm-svn: 299336
* [X86][MMX] Added support for subvector extraction to MMX registerSimon Pilgrim2017-04-022-7/+7
| | | | llvm-svn: 299335
* APInt.h: Prune \param(s) in \returns. [-Wdocumentation]NAKAMURA Takumi2017-04-021-1/+1
| | | | llvm-svn: 299334
* Regenerate test with codegen. NFCI.Simon Pilgrim2017-04-021-4/+10
| | | | llvm-svn: 299333
* Regenerate test with codegen. NFCI.Simon Pilgrim2017-04-021-4/+89
| | | | llvm-svn: 299332
* Regenerate test. NFCI.Simon Pilgrim2017-04-021-56/+56
| | | | llvm-svn: 299331
* NewGVN: Handle coercion of constant stores, loads, memory insts.Daniel Berlin2017-04-026-6/+152
| | | | | | | | | | | | | | | | | Summary: Depends on D30928. This adds support for coercion of stores and memory instructions that do not require insertion to process. Another few tests down. I added the relevant tests from rle.ll Reviewers: davide Subscribers: llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D30929 llvm-svn: 299330
* [BypassSlowDivision] Do not bypass division of hash-like valuesNikolai Bozhenov2017-04-022-12/+202
| | | | | | | | | | | | | | | | | Disable bypassing if one of the operands looks like a hash value. Slow division often occurs in hashtable implementations and fast division is never taken there because a hash value is extremely unlikely to have enough upper bits set to zero. A value is considered to be hash-like if it is produced by 1) XOR operation 2) Multiplication by a constant wider than the shorter type 3) PHI node with all incoming values being hash-like Differential Revision: https://reviews.llvm.org/D28200 llvm-svn: 299329
* [X86][MMX] Add generic fptosi 4f32-4i32 testSimon Pilgrim2017-04-021-0/+39
| | | | llvm-svn: 299328
* Add another interesting shufflevector test case for InstSimplify. NFC.Zvi Rackover2017-04-021-0/+9
| | | | | | | Test case shows opportunity to constant fold a shuffle with one variable input vector operand. llvm-svn: 299327
* [X86] Use tcAdd/tcSubtract to implement the slow case of operator+=/operator-=.Craig Topper2017-04-021-33/+3
| | | | llvm-svn: 299326
* [APInt] Combine declaration and initialization. NFCCraig Topper2017-04-021-6/+2
| | | | llvm-svn: 299325
* [APInt] Simplify some code by using operator+=(uint64_t) instead of doing a ↵Craig Topper2017-04-021-7/+2
| | | | | | more complex assignment into a temporary APInt just to use the APInt operator+=. llvm-svn: 299324
* [APInt] Fix typo in comment. NFCCraig Topper2017-04-021-1/+1
| | | | llvm-svn: 299323
* MemorySSA: Add support for caching clobbering access in storesDaniel Berlin2017-04-023-24/+55
| | | | | | | | | | | | | | | | Summary: This enables us to cache the clobbering access for stores, despite the fact that we can't rewrite the use-def chains themselves. Early testing shows that, after this change, for larger testcases, it will be a significant net positive (memory and time) to remove the walker caching. Reviewers: george.burgess.iv, davide Subscribers: Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D31567 llvm-svn: 299322
* [APInt] Use conditional operator to simplify some code. NFCCraig Topper2017-04-011-4/+1
| | | | llvm-svn: 299320
* [APInt] Implement flipAllBitsSlowCase with tcComplement. NFCICraig Topper2017-04-011-2/+1
| | | | llvm-svn: 299319
* [APInt] Fix indentation. NFCCraig Topper2017-04-011-8/+8
| | | | llvm-svn: 299318
* [APInt] Implement AndAssignSlowCase using tcAnd. Do the same for Or and Xor. ↵Craig Topper2017-04-011-9/+3
| | | | | | NFCI llvm-svn: 299317
* [APInt] Allow GreatestCommonDivisor to take rvalue inputs efficiently. Use ↵Craig Topper2017-04-012-8/+6
| | | | | | | | | | | | | | | | | | | moves instead of copies in the loop. Summary: GreatestComonDivisor currently makes a copy of both its inputs. Then in the loop we do one move and two copies, plus any allocation the urem call does. This patch changes it to take its inputs by value so that we can do a move of any rvalue inputs instead of copying. Then in the loop we do 3 move assignments and no copies. This way the only possible allocations we have in the loop is from the urem call. Reviewers: dblaikie, RKSimon, hans Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31572 llvm-svn: 299314
* [WASM] Remove other comparison of unsigned expression >= 0.Davide Italiano2017-04-011-3/+3
| | | | | | This should finally fix the GCC 7 build with -Werror. llvm-svn: 299313
* [WASM] Remove a set but never used variable.Davide Italiano2017-04-011-4/+1
| | | | llvm-svn: 299312
* [WASM] Remove an assertion that can never fire.Davide Italiano2017-04-011-2/+2
| | | | | | uint* is by definition always >=0. llvm-svn: 299311
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